blake2s_amd64.s (15876B)
1 // Copyright 2016 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 //go:build amd64 && gc && !purego 6 // +build amd64,gc,!purego 7 8 #include "textflag.h" 9 10 DATA iv0<>+0x00(SB)/4, $0x6a09e667 11 DATA iv0<>+0x04(SB)/4, $0xbb67ae85 12 DATA iv0<>+0x08(SB)/4, $0x3c6ef372 13 DATA iv0<>+0x0c(SB)/4, $0xa54ff53a 14 GLOBL iv0<>(SB), (NOPTR+RODATA), $16 15 16 DATA iv1<>+0x00(SB)/4, $0x510e527f 17 DATA iv1<>+0x04(SB)/4, $0x9b05688c 18 DATA iv1<>+0x08(SB)/4, $0x1f83d9ab 19 DATA iv1<>+0x0c(SB)/4, $0x5be0cd19 20 GLOBL iv1<>(SB), (NOPTR+RODATA), $16 21 22 DATA rol16<>+0x00(SB)/8, $0x0504070601000302 23 DATA rol16<>+0x08(SB)/8, $0x0D0C0F0E09080B0A 24 GLOBL rol16<>(SB), (NOPTR+RODATA), $16 25 26 DATA rol8<>+0x00(SB)/8, $0x0407060500030201 27 DATA rol8<>+0x08(SB)/8, $0x0C0F0E0D080B0A09 28 GLOBL rol8<>(SB), (NOPTR+RODATA), $16 29 30 DATA counter<>+0x00(SB)/8, $0x40 31 DATA counter<>+0x08(SB)/8, $0x0 32 GLOBL counter<>(SB), (NOPTR+RODATA), $16 33 34 #define ROTL_SSE2(n, t, v) \ 35 MOVO v, t; \ 36 PSLLL $n, t; \ 37 PSRLL $(32-n), v; \ 38 PXOR t, v 39 40 #define ROTL_SSSE3(c, v) \ 41 PSHUFB c, v 42 43 #define ROUND_SSE2(v0, v1, v2, v3, m0, m1, m2, m3, t) \ 44 PADDL m0, v0; \ 45 PADDL v1, v0; \ 46 PXOR v0, v3; \ 47 ROTL_SSE2(16, t, v3); \ 48 PADDL v3, v2; \ 49 PXOR v2, v1; \ 50 ROTL_SSE2(20, t, v1); \ 51 PADDL m1, v0; \ 52 PADDL v1, v0; \ 53 PXOR v0, v3; \ 54 ROTL_SSE2(24, t, v3); \ 55 PADDL v3, v2; \ 56 PXOR v2, v1; \ 57 ROTL_SSE2(25, t, v1); \ 58 PSHUFL $0x39, v1, v1; \ 59 PSHUFL $0x4E, v2, v2; \ 60 PSHUFL $0x93, v3, v3; \ 61 PADDL m2, v0; \ 62 PADDL v1, v0; \ 63 PXOR v0, v3; \ 64 ROTL_SSE2(16, t, v3); \ 65 PADDL v3, v2; \ 66 PXOR v2, v1; \ 67 ROTL_SSE2(20, t, v1); \ 68 PADDL m3, v0; \ 69 PADDL v1, v0; \ 70 PXOR v0, v3; \ 71 ROTL_SSE2(24, t, v3); \ 72 PADDL v3, v2; \ 73 PXOR v2, v1; \ 74 ROTL_SSE2(25, t, v1); \ 75 PSHUFL $0x39, v3, v3; \ 76 PSHUFL $0x4E, v2, v2; \ 77 PSHUFL $0x93, v1, v1 78 79 #define ROUND_SSSE3(v0, v1, v2, v3, m0, m1, m2, m3, t, c16, c8) \ 80 PADDL m0, v0; \ 81 PADDL v1, v0; \ 82 PXOR v0, v3; \ 83 ROTL_SSSE3(c16, v3); \ 84 PADDL v3, v2; \ 85 PXOR v2, v1; \ 86 ROTL_SSE2(20, t, v1); \ 87 PADDL m1, v0; \ 88 PADDL v1, v0; \ 89 PXOR v0, v3; \ 90 ROTL_SSSE3(c8, v3); \ 91 PADDL v3, v2; \ 92 PXOR v2, v1; \ 93 ROTL_SSE2(25, t, v1); \ 94 PSHUFL $0x39, v1, v1; \ 95 PSHUFL $0x4E, v2, v2; \ 96 PSHUFL $0x93, v3, v3; \ 97 PADDL m2, v0; \ 98 PADDL v1, v0; \ 99 PXOR v0, v3; \ 100 ROTL_SSSE3(c16, v3); \ 101 PADDL v3, v2; \ 102 PXOR v2, v1; \ 103 ROTL_SSE2(20, t, v1); \ 104 PADDL m3, v0; \ 105 PADDL v1, v0; \ 106 PXOR v0, v3; \ 107 ROTL_SSSE3(c8, v3); \ 108 PADDL v3, v2; \ 109 PXOR v2, v1; \ 110 ROTL_SSE2(25, t, v1); \ 111 PSHUFL $0x39, v3, v3; \ 112 PSHUFL $0x4E, v2, v2; \ 113 PSHUFL $0x93, v1, v1 114 115 116 #define LOAD_MSG_SSE4(m0, m1, m2, m3, src, i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15) \ 117 MOVL i0*4(src), m0; \ 118 PINSRD $1, i1*4(src), m0; \ 119 PINSRD $2, i2*4(src), m0; \ 120 PINSRD $3, i3*4(src), m0; \ 121 MOVL i4*4(src), m1; \ 122 PINSRD $1, i5*4(src), m1; \ 123 PINSRD $2, i6*4(src), m1; \ 124 PINSRD $3, i7*4(src), m1; \ 125 MOVL i8*4(src), m2; \ 126 PINSRD $1, i9*4(src), m2; \ 127 PINSRD $2, i10*4(src), m2; \ 128 PINSRD $3, i11*4(src), m2; \ 129 MOVL i12*4(src), m3; \ 130 PINSRD $1, i13*4(src), m3; \ 131 PINSRD $2, i14*4(src), m3; \ 132 PINSRD $3, i15*4(src), m3 133 134 #define PRECOMPUTE_MSG(dst, off, src, R8, R9, R10, R11, R12, R13, R14, R15) \ 135 MOVQ 0*4(src), R8; \ 136 MOVQ 2*4(src), R9; \ 137 MOVQ 4*4(src), R10; \ 138 MOVQ 6*4(src), R11; \ 139 MOVQ 8*4(src), R12; \ 140 MOVQ 10*4(src), R13; \ 141 MOVQ 12*4(src), R14; \ 142 MOVQ 14*4(src), R15; \ 143 \ 144 MOVL R8, 0*4+off+0(dst); \ 145 MOVL R8, 9*4+off+64(dst); \ 146 MOVL R8, 5*4+off+128(dst); \ 147 MOVL R8, 14*4+off+192(dst); \ 148 MOVL R8, 4*4+off+256(dst); \ 149 MOVL R8, 2*4+off+320(dst); \ 150 MOVL R8, 8*4+off+384(dst); \ 151 MOVL R8, 12*4+off+448(dst); \ 152 MOVL R8, 3*4+off+512(dst); \ 153 MOVL R8, 15*4+off+576(dst); \ 154 SHRQ $32, R8; \ 155 MOVL R8, 4*4+off+0(dst); \ 156 MOVL R8, 8*4+off+64(dst); \ 157 MOVL R8, 14*4+off+128(dst); \ 158 MOVL R8, 5*4+off+192(dst); \ 159 MOVL R8, 12*4+off+256(dst); \ 160 MOVL R8, 11*4+off+320(dst); \ 161 MOVL R8, 1*4+off+384(dst); \ 162 MOVL R8, 6*4+off+448(dst); \ 163 MOVL R8, 10*4+off+512(dst); \ 164 MOVL R8, 3*4+off+576(dst); \ 165 \ 166 MOVL R9, 1*4+off+0(dst); \ 167 MOVL R9, 13*4+off+64(dst); \ 168 MOVL R9, 6*4+off+128(dst); \ 169 MOVL R9, 8*4+off+192(dst); \ 170 MOVL R9, 2*4+off+256(dst); \ 171 MOVL R9, 0*4+off+320(dst); \ 172 MOVL R9, 14*4+off+384(dst); \ 173 MOVL R9, 11*4+off+448(dst); \ 174 MOVL R9, 12*4+off+512(dst); \ 175 MOVL R9, 4*4+off+576(dst); \ 176 SHRQ $32, R9; \ 177 MOVL R9, 5*4+off+0(dst); \ 178 MOVL R9, 15*4+off+64(dst); \ 179 MOVL R9, 9*4+off+128(dst); \ 180 MOVL R9, 1*4+off+192(dst); \ 181 MOVL R9, 11*4+off+256(dst); \ 182 MOVL R9, 7*4+off+320(dst); \ 183 MOVL R9, 13*4+off+384(dst); \ 184 MOVL R9, 3*4+off+448(dst); \ 185 MOVL R9, 6*4+off+512(dst); \ 186 MOVL R9, 10*4+off+576(dst); \ 187 \ 188 MOVL R10, 2*4+off+0(dst); \ 189 MOVL R10, 1*4+off+64(dst); \ 190 MOVL R10, 15*4+off+128(dst); \ 191 MOVL R10, 10*4+off+192(dst); \ 192 MOVL R10, 6*4+off+256(dst); \ 193 MOVL R10, 8*4+off+320(dst); \ 194 MOVL R10, 3*4+off+384(dst); \ 195 MOVL R10, 13*4+off+448(dst); \ 196 MOVL R10, 14*4+off+512(dst); \ 197 MOVL R10, 5*4+off+576(dst); \ 198 SHRQ $32, R10; \ 199 MOVL R10, 6*4+off+0(dst); \ 200 MOVL R10, 11*4+off+64(dst); \ 201 MOVL R10, 2*4+off+128(dst); \ 202 MOVL R10, 9*4+off+192(dst); \ 203 MOVL R10, 1*4+off+256(dst); \ 204 MOVL R10, 13*4+off+320(dst); \ 205 MOVL R10, 4*4+off+384(dst); \ 206 MOVL R10, 8*4+off+448(dst); \ 207 MOVL R10, 15*4+off+512(dst); \ 208 MOVL R10, 7*4+off+576(dst); \ 209 \ 210 MOVL R11, 3*4+off+0(dst); \ 211 MOVL R11, 7*4+off+64(dst); \ 212 MOVL R11, 13*4+off+128(dst); \ 213 MOVL R11, 12*4+off+192(dst); \ 214 MOVL R11, 10*4+off+256(dst); \ 215 MOVL R11, 1*4+off+320(dst); \ 216 MOVL R11, 9*4+off+384(dst); \ 217 MOVL R11, 14*4+off+448(dst); \ 218 MOVL R11, 0*4+off+512(dst); \ 219 MOVL R11, 6*4+off+576(dst); \ 220 SHRQ $32, R11; \ 221 MOVL R11, 7*4+off+0(dst); \ 222 MOVL R11, 14*4+off+64(dst); \ 223 MOVL R11, 10*4+off+128(dst); \ 224 MOVL R11, 0*4+off+192(dst); \ 225 MOVL R11, 5*4+off+256(dst); \ 226 MOVL R11, 9*4+off+320(dst); \ 227 MOVL R11, 12*4+off+384(dst); \ 228 MOVL R11, 1*4+off+448(dst); \ 229 MOVL R11, 13*4+off+512(dst); \ 230 MOVL R11, 2*4+off+576(dst); \ 231 \ 232 MOVL R12, 8*4+off+0(dst); \ 233 MOVL R12, 5*4+off+64(dst); \ 234 MOVL R12, 4*4+off+128(dst); \ 235 MOVL R12, 15*4+off+192(dst); \ 236 MOVL R12, 14*4+off+256(dst); \ 237 MOVL R12, 3*4+off+320(dst); \ 238 MOVL R12, 11*4+off+384(dst); \ 239 MOVL R12, 10*4+off+448(dst); \ 240 MOVL R12, 7*4+off+512(dst); \ 241 MOVL R12, 1*4+off+576(dst); \ 242 SHRQ $32, R12; \ 243 MOVL R12, 12*4+off+0(dst); \ 244 MOVL R12, 2*4+off+64(dst); \ 245 MOVL R12, 11*4+off+128(dst); \ 246 MOVL R12, 4*4+off+192(dst); \ 247 MOVL R12, 0*4+off+256(dst); \ 248 MOVL R12, 15*4+off+320(dst); \ 249 MOVL R12, 10*4+off+384(dst); \ 250 MOVL R12, 7*4+off+448(dst); \ 251 MOVL R12, 5*4+off+512(dst); \ 252 MOVL R12, 9*4+off+576(dst); \ 253 \ 254 MOVL R13, 9*4+off+0(dst); \ 255 MOVL R13, 4*4+off+64(dst); \ 256 MOVL R13, 8*4+off+128(dst); \ 257 MOVL R13, 13*4+off+192(dst); \ 258 MOVL R13, 3*4+off+256(dst); \ 259 MOVL R13, 5*4+off+320(dst); \ 260 MOVL R13, 7*4+off+384(dst); \ 261 MOVL R13, 15*4+off+448(dst); \ 262 MOVL R13, 11*4+off+512(dst); \ 263 MOVL R13, 0*4+off+576(dst); \ 264 SHRQ $32, R13; \ 265 MOVL R13, 13*4+off+0(dst); \ 266 MOVL R13, 10*4+off+64(dst); \ 267 MOVL R13, 0*4+off+128(dst); \ 268 MOVL R13, 3*4+off+192(dst); \ 269 MOVL R13, 9*4+off+256(dst); \ 270 MOVL R13, 6*4+off+320(dst); \ 271 MOVL R13, 15*4+off+384(dst); \ 272 MOVL R13, 4*4+off+448(dst); \ 273 MOVL R13, 2*4+off+512(dst); \ 274 MOVL R13, 12*4+off+576(dst); \ 275 \ 276 MOVL R14, 10*4+off+0(dst); \ 277 MOVL R14, 12*4+off+64(dst); \ 278 MOVL R14, 1*4+off+128(dst); \ 279 MOVL R14, 6*4+off+192(dst); \ 280 MOVL R14, 13*4+off+256(dst); \ 281 MOVL R14, 4*4+off+320(dst); \ 282 MOVL R14, 0*4+off+384(dst); \ 283 MOVL R14, 2*4+off+448(dst); \ 284 MOVL R14, 8*4+off+512(dst); \ 285 MOVL R14, 14*4+off+576(dst); \ 286 SHRQ $32, R14; \ 287 MOVL R14, 14*4+off+0(dst); \ 288 MOVL R14, 3*4+off+64(dst); \ 289 MOVL R14, 7*4+off+128(dst); \ 290 MOVL R14, 2*4+off+192(dst); \ 291 MOVL R14, 15*4+off+256(dst); \ 292 MOVL R14, 12*4+off+320(dst); \ 293 MOVL R14, 6*4+off+384(dst); \ 294 MOVL R14, 0*4+off+448(dst); \ 295 MOVL R14, 9*4+off+512(dst); \ 296 MOVL R14, 11*4+off+576(dst); \ 297 \ 298 MOVL R15, 11*4+off+0(dst); \ 299 MOVL R15, 0*4+off+64(dst); \ 300 MOVL R15, 12*4+off+128(dst); \ 301 MOVL R15, 7*4+off+192(dst); \ 302 MOVL R15, 8*4+off+256(dst); \ 303 MOVL R15, 14*4+off+320(dst); \ 304 MOVL R15, 2*4+off+384(dst); \ 305 MOVL R15, 5*4+off+448(dst); \ 306 MOVL R15, 1*4+off+512(dst); \ 307 MOVL R15, 13*4+off+576(dst); \ 308 SHRQ $32, R15; \ 309 MOVL R15, 15*4+off+0(dst); \ 310 MOVL R15, 6*4+off+64(dst); \ 311 MOVL R15, 3*4+off+128(dst); \ 312 MOVL R15, 11*4+off+192(dst); \ 313 MOVL R15, 7*4+off+256(dst); \ 314 MOVL R15, 10*4+off+320(dst); \ 315 MOVL R15, 5*4+off+384(dst); \ 316 MOVL R15, 9*4+off+448(dst); \ 317 MOVL R15, 4*4+off+512(dst); \ 318 MOVL R15, 8*4+off+576(dst) 319 320 #define BLAKE2s_SSE2() \ 321 PRECOMPUTE_MSG(BP, 16, SI, R8, R9, R10, R11, R12, R13, R14, R15); \ 322 ROUND_SSE2(X4, X5, X6, X7, 16(BP), 32(BP), 48(BP), 64(BP), X8); \ 323 ROUND_SSE2(X4, X5, X6, X7, 16+64(BP), 32+64(BP), 48+64(BP), 64+64(BP), X8); \ 324 ROUND_SSE2(X4, X5, X6, X7, 16+128(BP), 32+128(BP), 48+128(BP), 64+128(BP), X8); \ 325 ROUND_SSE2(X4, X5, X6, X7, 16+192(BP), 32+192(BP), 48+192(BP), 64+192(BP), X8); \ 326 ROUND_SSE2(X4, X5, X6, X7, 16+256(BP), 32+256(BP), 48+256(BP), 64+256(BP), X8); \ 327 ROUND_SSE2(X4, X5, X6, X7, 16+320(BP), 32+320(BP), 48+320(BP), 64+320(BP), X8); \ 328 ROUND_SSE2(X4, X5, X6, X7, 16+384(BP), 32+384(BP), 48+384(BP), 64+384(BP), X8); \ 329 ROUND_SSE2(X4, X5, X6, X7, 16+448(BP), 32+448(BP), 48+448(BP), 64+448(BP), X8); \ 330 ROUND_SSE2(X4, X5, X6, X7, 16+512(BP), 32+512(BP), 48+512(BP), 64+512(BP), X8); \ 331 ROUND_SSE2(X4, X5, X6, X7, 16+576(BP), 32+576(BP), 48+576(BP), 64+576(BP), X8) 332 333 #define BLAKE2s_SSSE3() \ 334 PRECOMPUTE_MSG(BP, 16, SI, R8, R9, R10, R11, R12, R13, R14, R15); \ 335 ROUND_SSSE3(X4, X5, X6, X7, 16(BP), 32(BP), 48(BP), 64(BP), X8, X13, X14); \ 336 ROUND_SSSE3(X4, X5, X6, X7, 16+64(BP), 32+64(BP), 48+64(BP), 64+64(BP), X8, X13, X14); \ 337 ROUND_SSSE3(X4, X5, X6, X7, 16+128(BP), 32+128(BP), 48+128(BP), 64+128(BP), X8, X13, X14); \ 338 ROUND_SSSE3(X4, X5, X6, X7, 16+192(BP), 32+192(BP), 48+192(BP), 64+192(BP), X8, X13, X14); \ 339 ROUND_SSSE3(X4, X5, X6, X7, 16+256(BP), 32+256(BP), 48+256(BP), 64+256(BP), X8, X13, X14); \ 340 ROUND_SSSE3(X4, X5, X6, X7, 16+320(BP), 32+320(BP), 48+320(BP), 64+320(BP), X8, X13, X14); \ 341 ROUND_SSSE3(X4, X5, X6, X7, 16+384(BP), 32+384(BP), 48+384(BP), 64+384(BP), X8, X13, X14); \ 342 ROUND_SSSE3(X4, X5, X6, X7, 16+448(BP), 32+448(BP), 48+448(BP), 64+448(BP), X8, X13, X14); \ 343 ROUND_SSSE3(X4, X5, X6, X7, 16+512(BP), 32+512(BP), 48+512(BP), 64+512(BP), X8, X13, X14); \ 344 ROUND_SSSE3(X4, X5, X6, X7, 16+576(BP), 32+576(BP), 48+576(BP), 64+576(BP), X8, X13, X14) 345 346 #define BLAKE2s_SSE4() \ 347 LOAD_MSG_SSE4(X8, X9, X10, X11, SI, 0, 2, 4, 6, 1, 3, 5, 7, 8, 10, 12, 14, 9, 11, 13, 15); \ 348 ROUND_SSSE3(X4, X5, X6, X7, X8, X9, X10, X11, X8, X13, X14); \ 349 LOAD_MSG_SSE4(X8, X9, X10, X11, SI, 14, 4, 9, 13, 10, 8, 15, 6, 1, 0, 11, 5, 12, 2, 7, 3); \ 350 ROUND_SSSE3(X4, X5, X6, X7, X8, X9, X10, X11, X8, X13, X14); \ 351 LOAD_MSG_SSE4(X8, X9, X10, X11, SI, 11, 12, 5, 15, 8, 0, 2, 13, 10, 3, 7, 9, 14, 6, 1, 4); \ 352 ROUND_SSSE3(X4, X5, X6, X7, X8, X9, X10, X11, X8, X13, X14); \ 353 LOAD_MSG_SSE4(X8, X9, X10, X11, SI, 7, 3, 13, 11, 9, 1, 12, 14, 2, 5, 4, 15, 6, 10, 0, 8); \ 354 ROUND_SSSE3(X4, X5, X6, X7, X8, X9, X10, X11, X8, X13, X14); \ 355 LOAD_MSG_SSE4(X8, X9, X10, X11, SI, 9, 5, 2, 10, 0, 7, 4, 15, 14, 11, 6, 3, 1, 12, 8, 13); \ 356 ROUND_SSSE3(X4, X5, X6, X7, X8, X9, X10, X11, X8, X13, X14); \ 357 LOAD_MSG_SSE4(X8, X9, X10, X11, SI, 2, 6, 0, 8, 12, 10, 11, 3, 4, 7, 15, 1, 13, 5, 14, 9); \ 358 ROUND_SSSE3(X4, X5, X6, X7, X8, X9, X10, X11, X8, X13, X14); \ 359 LOAD_MSG_SSE4(X8, X9, X10, X11, SI, 12, 1, 14, 4, 5, 15, 13, 10, 0, 6, 9, 8, 7, 3, 2, 11); \ 360 ROUND_SSSE3(X4, X5, X6, X7, X8, X9, X10, X11, X8, X13, X14); \ 361 LOAD_MSG_SSE4(X8, X9, X10, X11, SI, 13, 7, 12, 3, 11, 14, 1, 9, 5, 15, 8, 2, 0, 4, 6, 10); \ 362 ROUND_SSSE3(X4, X5, X6, X7, X8, X9, X10, X11, X8, X13, X14); \ 363 LOAD_MSG_SSE4(X8, X9, X10, X11, SI, 6, 14, 11, 0, 15, 9, 3, 8, 12, 13, 1, 10, 2, 7, 4, 5); \ 364 ROUND_SSSE3(X4, X5, X6, X7, X8, X9, X10, X11, X8, X13, X14); \ 365 LOAD_MSG_SSE4(X8, X9, X10, X11, SI, 10, 8, 7, 1, 2, 4, 6, 5, 15, 9, 3, 13, 11, 14, 12, 0); \ 366 ROUND_SSSE3(X4, X5, X6, X7, X8, X9, X10, X11, X8, X13, X14) 367 368 #define HASH_BLOCKS(h, c, flag, blocks_base, blocks_len, BLAKE2s_FUNC) \ 369 MOVQ h, AX; \ 370 MOVQ c, BX; \ 371 MOVL flag, CX; \ 372 MOVQ blocks_base, SI; \ 373 MOVQ blocks_len, DX; \ 374 \ 375 MOVQ SP, BP; \ 376 ADDQ $15, BP; \ 377 ANDQ $~15, BP; \ 378 \ 379 MOVQ 0(BX), R9; \ 380 MOVQ R9, 0(BP); \ 381 MOVQ CX, 8(BP); \ 382 \ 383 MOVOU 0(AX), X0; \ 384 MOVOU 16(AX), X1; \ 385 MOVOU iv0<>(SB), X2; \ 386 MOVOU iv1<>(SB), X3 \ 387 \ 388 MOVOU counter<>(SB), X12; \ 389 MOVOU rol16<>(SB), X13; \ 390 MOVOU rol8<>(SB), X14; \ 391 MOVO 0(BP), X15; \ 392 \ 393 loop: \ 394 MOVO X0, X4; \ 395 MOVO X1, X5; \ 396 MOVO X2, X6; \ 397 MOVO X3, X7; \ 398 \ 399 PADDQ X12, X15; \ 400 PXOR X15, X7; \ 401 \ 402 BLAKE2s_FUNC(); \ 403 \ 404 PXOR X4, X0; \ 405 PXOR X5, X1; \ 406 PXOR X6, X0; \ 407 PXOR X7, X1; \ 408 \ 409 LEAQ 64(SI), SI; \ 410 SUBQ $64, DX; \ 411 JNE loop; \ 412 \ 413 MOVO X15, 0(BP); \ 414 MOVQ 0(BP), R9; \ 415 MOVQ R9, 0(BX); \ 416 \ 417 MOVOU X0, 0(AX); \ 418 MOVOU X1, 16(AX) 419 420 // func hashBlocksSSE2(h *[8]uint32, c *[2]uint32, flag uint32, blocks []byte) 421 TEXT ·hashBlocksSSE2(SB), 0, $672-48 // frame = 656 + 16 byte alignment 422 HASH_BLOCKS(h+0(FP), c+8(FP), flag+16(FP), blocks_base+24(FP), blocks_len+32(FP), BLAKE2s_SSE2) 423 RET 424 425 // func hashBlocksSSSE3(h *[8]uint32, c *[2]uint32, flag uint32, blocks []byte) 426 TEXT ·hashBlocksSSSE3(SB), 0, $672-48 // frame = 656 + 16 byte alignment 427 HASH_BLOCKS(h+0(FP), c+8(FP), flag+16(FP), blocks_base+24(FP), blocks_len+32(FP), BLAKE2s_SSSE3) 428 RET 429 430 // func hashBlocksSSE4(h *[8]uint32, c *[2]uint32, flag uint32, blocks []byte) 431 TEXT ·hashBlocksSSE4(SB), 0, $32-48 // frame = 16 + 16 byte alignment 432 HASH_BLOCKS(h+0(FP), c+8(FP), flag+16(FP), blocks_base+24(FP), blocks_len+32(FP), BLAKE2s_SSE4) 433 RET