asmz.go (177957B)
1 // Based on cmd/internal/obj/ppc64/asm9.go. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package s390x 31 32 import ( 33 "github.com/twitchyliquid64/golang-asm/obj" 34 "github.com/twitchyliquid64/golang-asm/objabi" 35 "fmt" 36 "log" 37 "math" 38 "sort" 39 ) 40 41 // ctxtz holds state while assembling a single function. 42 // Each function gets a fresh ctxtz. 43 // This allows for multiple functions to be safely concurrently assembled. 44 type ctxtz struct { 45 ctxt *obj.Link 46 newprog obj.ProgAlloc 47 cursym *obj.LSym 48 autosize int32 49 instoffset int64 50 pc int64 51 } 52 53 // instruction layout. 54 const ( 55 funcAlign = 16 56 ) 57 58 type Optab struct { 59 as obj.As // opcode 60 i uint8 // handler index 61 a1 uint8 // From 62 a2 uint8 // Reg 63 a3 uint8 // RestArgs[0] 64 a4 uint8 // RestArgs[1] 65 a5 uint8 // RestArgs[2] 66 a6 uint8 // To 67 } 68 69 var optab = []Optab{ 70 // zero-length instructions 71 {i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE}, 72 {i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE}, 73 {i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON}, 74 {i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR}, 75 {i: 0, as: obj.ANOP}, 76 {i: 0, as: obj.ANOP, a1: C_SAUTO}, 77 78 // move register 79 {i: 1, as: AMOVD, a1: C_REG, a6: C_REG}, 80 {i: 1, as: AMOVB, a1: C_REG, a6: C_REG}, 81 {i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG}, 82 {i: 1, as: AMOVW, a1: C_REG, a6: C_REG}, 83 {i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG}, 84 {i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG}, 85 {i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG}, 86 87 // load constant 88 {i: 26, as: AMOVD, a1: C_LACON, a6: C_REG}, 89 {i: 26, as: AMOVW, a1: C_LACON, a6: C_REG}, 90 {i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG}, 91 {i: 3, as: AMOVD, a1: C_DCON, a6: C_REG}, 92 {i: 3, as: AMOVW, a1: C_DCON, a6: C_REG}, 93 {i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG}, 94 {i: 3, as: AMOVB, a1: C_DCON, a6: C_REG}, 95 {i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG}, 96 97 // store constant 98 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO}, 99 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO}, 100 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO}, 101 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO}, 102 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO}, 103 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO}, 104 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO}, 105 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO}, 106 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO}, 107 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO}, 108 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG}, 109 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG}, 110 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG}, 111 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG}, 112 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG}, 113 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG}, 114 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG}, 115 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG}, 116 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG}, 117 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG}, 118 119 // store 120 {i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO}, 121 {i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO}, 122 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO}, 123 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO}, 124 {i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO}, 125 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO}, 126 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO}, 127 {i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG}, 128 {i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG}, 129 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG}, 130 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG}, 131 {i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG}, 132 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG}, 133 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG}, 134 {i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR}, 135 {i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR}, 136 {i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR}, 137 {i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR}, 138 {i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR}, 139 140 // load 141 {i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG}, 142 {i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG}, 143 {i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG}, 144 {i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG}, 145 {i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG}, 146 {i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG}, 147 {i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG}, 148 {i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG}, 149 {i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG}, 150 {i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG}, 151 {i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG}, 152 {i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG}, 153 {i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG}, 154 {i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG}, 155 {i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG}, 156 {i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG}, 157 {i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG}, 158 {i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG}, 159 {i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG}, 160 161 // interlocked load and op 162 {i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG}, 163 164 // integer arithmetic 165 {i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG}, 166 {i: 2, as: AADD, a1: C_REG, a6: C_REG}, 167 {i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG}, 168 {i: 22, as: AADD, a1: C_LCON, a6: C_REG}, 169 {i: 12, as: AADD, a1: C_LOREG, a6: C_REG}, 170 {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG}, 171 {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG}, 172 {i: 21, as: ASUB, a1: C_LCON, a6: C_REG}, 173 {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG}, 174 {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG}, 175 {i: 4, as: AMULHD, a1: C_REG, a6: C_REG}, 176 {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG}, 177 {i: 62, as: AMLGR, a1: C_REG, a6: C_REG}, 178 {i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG}, 179 {i: 2, as: ADIVW, a1: C_REG, a6: C_REG}, 180 {i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG}, 181 {i: 10, as: ASUB, a1: C_REG, a6: C_REG}, 182 {i: 47, as: ANEG, a1: C_REG, a6: C_REG}, 183 {i: 47, as: ANEG, a6: C_REG}, 184 185 // integer logical 186 {i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG}, 187 {i: 6, as: AAND, a1: C_REG, a6: C_REG}, 188 {i: 23, as: AAND, a1: C_LCON, a6: C_REG}, 189 {i: 12, as: AAND, a1: C_LOREG, a6: C_REG}, 190 {i: 12, as: AAND, a1: C_LAUTO, a6: C_REG}, 191 {i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG}, 192 {i: 6, as: AANDW, a1: C_REG, a6: C_REG}, 193 {i: 24, as: AANDW, a1: C_LCON, a6: C_REG}, 194 {i: 12, as: AANDW, a1: C_LOREG, a6: C_REG}, 195 {i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG}, 196 {i: 7, as: ASLD, a1: C_REG, a6: C_REG}, 197 {i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG}, 198 {i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG}, 199 {i: 7, as: ASLD, a1: C_SCON, a6: C_REG}, 200 {i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG}, 201 202 // compare and swap 203 {i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG}, 204 205 // floating point 206 {i: 32, as: AFADD, a1: C_FREG, a6: C_FREG}, 207 {i: 33, as: AFABS, a1: C_FREG, a6: C_FREG}, 208 {i: 33, as: AFABS, a6: C_FREG}, 209 {i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG}, 210 {i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG}, 211 {i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG}, 212 {i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG}, 213 {i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG}, 214 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO}, 215 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG}, 216 {i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR}, 217 {i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG}, 218 {i: 81, as: ALDGR, a1: C_REG, a6: C_FREG}, 219 {i: 81, as: ALGDR, a1: C_FREG, a6: C_REG}, 220 {i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG}, 221 {i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG}, 222 {i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG}, 223 {i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG}, 224 {i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG}, 225 {i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON}, 226 227 // load symbol address (plus offset) 228 {i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG}, 229 {i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG}, 230 {i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG}, 231 {i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG}, 232 233 // system call 234 {i: 5, as: ASYSCALL}, 235 {i: 77, as: ASYSCALL, a1: C_SCON}, 236 237 // branch 238 {i: 16, as: ABEQ, a6: C_SBRA}, 239 {i: 16, as: ABRC, a1: C_SCON, a6: C_SBRA}, 240 {i: 11, as: ABR, a6: C_LBRA}, 241 {i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA}, 242 {i: 18, as: ABR, a6: C_REG}, 243 {i: 18, as: ABR, a1: C_REG, a6: C_REG}, 244 {i: 15, as: ABR, a6: C_ZOREG}, 245 {i: 15, as: ABC, a6: C_ZOREG}, 246 247 // compare and branch 248 {i: 89, as: ACGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA}, 249 {i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA}, 250 {i: 89, as: ACLGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA}, 251 {i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA}, 252 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA}, 253 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_SCON, a6: C_SBRA}, 254 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA}, 255 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA}, 256 {i: 90, as: ACLGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA}, 257 {i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA}, 258 259 // branch on count 260 {i: 41, as: ABRCT, a1: C_REG, a6: C_SBRA}, 261 {i: 41, as: ABRCTG, a1: C_REG, a6: C_SBRA}, 262 263 // move on condition 264 {i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG}, 265 266 // load on condition 267 {i: 25, as: ALOCGR, a1: C_SCON, a2: C_REG, a6: C_REG}, 268 269 // find leftmost one 270 {i: 8, as: AFLOGR, a1: C_REG, a6: C_REG}, 271 272 // population count 273 {i: 9, as: APOPCNT, a1: C_REG, a6: C_REG}, 274 275 // compare 276 {i: 70, as: ACMP, a1: C_REG, a6: C_REG}, 277 {i: 71, as: ACMP, a1: C_REG, a6: C_LCON}, 278 {i: 70, as: ACMPU, a1: C_REG, a6: C_REG}, 279 {i: 71, as: ACMPU, a1: C_REG, a6: C_LCON}, 280 {i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG}, 281 {i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG}, 282 283 // test under mask 284 {i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON}, 285 286 // insert program mask 287 {i: 92, as: AIPM, a1: C_REG}, 288 289 // set program mask 290 {i: 76, as: ASPM, a1: C_REG}, 291 292 // 32-bit access registers 293 {i: 68, as: AMOVW, a1: C_AREG, a6: C_REG}, 294 {i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG}, 295 {i: 69, as: AMOVW, a1: C_REG, a6: C_AREG}, 296 {i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG}, 297 298 // macros 299 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG}, 300 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO}, 301 302 // load/store multiple 303 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG}, 304 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO}, 305 {i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG}, 306 {i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG}, 307 308 // bytes 309 {i: 40, as: ABYTE, a1: C_SCON}, 310 {i: 40, as: AWORD, a1: C_LCON}, 311 {i: 31, as: ADWORD, a1: C_LCON}, 312 {i: 31, as: ADWORD, a1: C_DCON}, 313 314 // fast synchronization 315 {i: 80, as: ASYNC}, 316 317 // store clock 318 {i: 88, as: ASTCK, a6: C_SAUTO}, 319 {i: 88, as: ASTCK, a6: C_SOREG}, 320 321 // storage and storage 322 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG}, 323 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO}, 324 {i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO}, 325 326 // address 327 {i: 85, as: ALARL, a1: C_LCON, a6: C_REG}, 328 {i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG}, 329 {i: 86, as: ALA, a1: C_SOREG, a6: C_REG}, 330 {i: 86, as: ALA, a1: C_SAUTO, a6: C_REG}, 331 {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG}, 332 333 // undefined (deliberate illegal instruction) 334 {i: 78, as: obj.AUNDEF}, 335 336 // 2 byte no-operation 337 {i: 66, as: ANOPH}, 338 339 // vector instructions 340 341 // VRX store 342 {i: 100, as: AVST, a1: C_VREG, a6: C_SOREG}, 343 {i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO}, 344 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG}, 345 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO}, 346 347 // VRX load 348 {i: 101, as: AVL, a1: C_SOREG, a6: C_VREG}, 349 {i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG}, 350 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG}, 351 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG}, 352 353 // VRV scatter 354 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG}, 355 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO}, 356 357 // VRV gather 358 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG}, 359 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG}, 360 361 // VRS element shift/rotate and load gr to/from vr element 362 {i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG}, 363 {i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG}, 364 {i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG}, 365 {i: 104, as: AVESLG, a1: C_REG, a6: C_VREG}, 366 {i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG}, 367 {i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG}, 368 {i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG}, 369 {i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG}, 370 371 // VRS store multiple 372 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG}, 373 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO}, 374 375 // VRS load multiple 376 {i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG}, 377 {i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG}, 378 379 // VRS store with length 380 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG}, 381 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO}, 382 383 // VRS load with length 384 {i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG}, 385 {i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG}, 386 387 // VRI-a 388 {i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG}, 389 {i: 109, as: AVZERO, a6: C_VREG}, 390 {i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG}, 391 {i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG}, 392 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG}, 393 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG}, 394 395 // VRI-b generate mask 396 {i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG}, 397 398 // VRI-c replicate 399 {i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG}, 400 401 // VRI-d element rotate and insert under mask and 402 // shift left double by byte 403 {i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 404 {i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 405 406 // VRI-d fp test data class immediate 407 {i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG}, 408 409 // VRR-a load reg 410 {i: 114, as: AVLR, a1: C_VREG, a6: C_VREG}, 411 412 // VRR-a compare 413 {i: 115, as: AVECG, a1: C_VREG, a6: C_VREG}, 414 415 // VRR-b 416 {i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 417 {i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 418 {i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 419 420 // VRR-c 421 {i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 422 {i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG}, 423 {i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG}, 424 {i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 425 426 // VRR-c shifts 427 {i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 428 {i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG}, 429 430 // VRR-d 431 {i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 432 433 // VRR-e 434 {i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 435 436 // VRR-f 437 {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG}, 438 } 439 440 var oprange [ALAST & obj.AMask][]Optab 441 442 var xcmp [C_NCLASS][C_NCLASS]bool 443 444 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 445 if ctxt.Retpoline { 446 ctxt.Diag("-spectre=ret not supported on s390x") 447 ctxt.Retpoline = false // don't keep printing 448 } 449 450 p := cursym.Func.Text 451 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 452 return 453 } 454 455 if oprange[AORW&obj.AMask] == nil { 456 ctxt.Diag("s390x ops not initialized, call s390x.buildop first") 457 } 458 459 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 460 461 buffer := make([]byte, 0) 462 changed := true 463 loop := 0 464 for changed { 465 if loop > 100 { 466 c.ctxt.Diag("stuck in spanz loop") 467 break 468 } 469 changed = false 470 buffer = buffer[:0] 471 c.cursym.R = make([]obj.Reloc, 0) 472 for p := c.cursym.Func.Text; p != nil; p = p.Link { 473 pc := int64(len(buffer)) 474 if pc != p.Pc { 475 changed = true 476 } 477 p.Pc = pc 478 c.pc = p.Pc 479 c.asmout(p, &buffer) 480 if pc == int64(len(buffer)) { 481 switch p.As { 482 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 483 // ok 484 default: 485 c.ctxt.Diag("zero-width instruction\n%v", p) 486 } 487 } 488 } 489 loop++ 490 } 491 492 c.cursym.Size = int64(len(buffer)) 493 if c.cursym.Size%funcAlign != 0 { 494 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign) 495 } 496 c.cursym.Grow(c.cursym.Size) 497 copy(c.cursym.P, buffer) 498 499 // Mark nonpreemptible instruction sequences. 500 // We use REGTMP as a scratch register during call injection, 501 // so instruction sequences that use REGTMP are unsafe to 502 // preempt asynchronously. 503 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func.Text, c.newprog, c.isUnsafePoint, nil) 504 } 505 506 // Return whether p is an unsafe point. 507 func (c *ctxtz) isUnsafePoint(p *obj.Prog) bool { 508 if p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP { 509 return true 510 } 511 for _, a := range p.RestArgs { 512 if a.Reg == REGTMP { 513 return true 514 } 515 } 516 return p.Mark&USETMP != 0 517 } 518 519 func isint32(v int64) bool { 520 return int64(int32(v)) == v 521 } 522 523 func isuint32(v uint64) bool { 524 return uint64(uint32(v)) == v 525 } 526 527 func (c *ctxtz) aclass(a *obj.Addr) int { 528 switch a.Type { 529 case obj.TYPE_NONE: 530 return C_NONE 531 532 case obj.TYPE_REG: 533 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 534 return C_REG 535 } 536 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 537 return C_FREG 538 } 539 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 540 return C_AREG 541 } 542 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 543 return C_VREG 544 } 545 return C_GOK 546 547 case obj.TYPE_MEM: 548 switch a.Name { 549 case obj.NAME_EXTERN, 550 obj.NAME_STATIC: 551 if a.Sym == nil { 552 // must have a symbol 553 break 554 } 555 c.instoffset = a.Offset 556 if a.Sym.Type == objabi.STLSBSS { 557 if c.ctxt.Flag_shared { 558 return C_TLS_IE // initial exec model 559 } 560 return C_TLS_LE // local exec model 561 } 562 return C_ADDR 563 564 case obj.NAME_GOTREF: 565 return C_GOTADDR 566 567 case obj.NAME_AUTO: 568 if a.Reg == REGSP { 569 // unset base register for better printing, since 570 // a.Offset is still relative to pseudo-SP. 571 a.Reg = obj.REG_NONE 572 } 573 c.instoffset = int64(c.autosize) + a.Offset 574 if c.instoffset >= -BIG && c.instoffset < BIG { 575 return C_SAUTO 576 } 577 return C_LAUTO 578 579 case obj.NAME_PARAM: 580 if a.Reg == REGSP { 581 // unset base register for better printing, since 582 // a.Offset is still relative to pseudo-FP. 583 a.Reg = obj.REG_NONE 584 } 585 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 586 if c.instoffset >= -BIG && c.instoffset < BIG { 587 return C_SAUTO 588 } 589 return C_LAUTO 590 591 case obj.NAME_NONE: 592 c.instoffset = a.Offset 593 if c.instoffset == 0 { 594 return C_ZOREG 595 } 596 if c.instoffset >= -BIG && c.instoffset < BIG { 597 return C_SOREG 598 } 599 return C_LOREG 600 } 601 602 return C_GOK 603 604 case obj.TYPE_TEXTSIZE: 605 return C_TEXTSIZE 606 607 case obj.TYPE_FCONST: 608 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 609 return C_ZCON 610 } 611 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val) 612 613 case obj.TYPE_CONST, 614 obj.TYPE_ADDR: 615 switch a.Name { 616 case obj.NAME_NONE: 617 c.instoffset = a.Offset 618 if a.Reg != 0 { 619 if -BIG <= c.instoffset && c.instoffset <= BIG { 620 return C_SACON 621 } 622 if isint32(c.instoffset) { 623 return C_LACON 624 } 625 return C_DACON 626 } 627 628 case obj.NAME_EXTERN, 629 obj.NAME_STATIC: 630 s := a.Sym 631 if s == nil { 632 return C_GOK 633 } 634 c.instoffset = a.Offset 635 636 return C_SYMADDR 637 638 case obj.NAME_AUTO: 639 if a.Reg == REGSP { 640 // unset base register for better printing, since 641 // a.Offset is still relative to pseudo-SP. 642 a.Reg = obj.REG_NONE 643 } 644 c.instoffset = int64(c.autosize) + a.Offset 645 if c.instoffset >= -BIG && c.instoffset < BIG { 646 return C_SACON 647 } 648 return C_LACON 649 650 case obj.NAME_PARAM: 651 if a.Reg == REGSP { 652 // unset base register for better printing, since 653 // a.Offset is still relative to pseudo-FP. 654 a.Reg = obj.REG_NONE 655 } 656 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 657 if c.instoffset >= -BIG && c.instoffset < BIG { 658 return C_SACON 659 } 660 return C_LACON 661 662 default: 663 return C_GOK 664 } 665 666 if c.instoffset == 0 { 667 return C_ZCON 668 } 669 if c.instoffset >= 0 { 670 if c.instoffset <= 0x7fff { 671 return C_SCON 672 } 673 if c.instoffset <= 0xffff { 674 return C_ANDCON 675 } 676 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 677 return C_UCON 678 } 679 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 680 return C_LCON 681 } 682 return C_DCON 683 } 684 685 if c.instoffset >= -0x8000 { 686 return C_ADDCON 687 } 688 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 689 return C_UCON 690 } 691 if isint32(c.instoffset) { 692 return C_LCON 693 } 694 return C_DCON 695 696 case obj.TYPE_BRANCH: 697 return C_SBRA 698 } 699 700 return C_GOK 701 } 702 703 func (c *ctxtz) oplook(p *obj.Prog) *Optab { 704 // Return cached optab entry if available. 705 if p.Optab != 0 { 706 return &optab[p.Optab-1] 707 } 708 if len(p.RestArgs) > 3 { 709 c.ctxt.Diag("too many RestArgs: got %v, maximum is 3\n", len(p.RestArgs)) 710 return nil 711 } 712 713 // Initialize classes for all arguments. 714 p.From.Class = int8(c.aclass(&p.From) + 1) 715 p.To.Class = int8(c.aclass(&p.To) + 1) 716 for i := range p.RestArgs { 717 p.RestArgs[i].Class = int8(c.aclass(&p.RestArgs[i]) + 1) 718 } 719 720 // Mirrors the argument list in Optab. 721 args := [...]int8{ 722 p.From.Class - 1, 723 C_NONE, // p.Reg 724 C_NONE, // p.RestArgs[0] 725 C_NONE, // p.RestArgs[1] 726 C_NONE, // p.RestArgs[2] 727 p.To.Class - 1, 728 } 729 // Fill in argument class for p.Reg. 730 switch { 731 case REG_R0 <= p.Reg && p.Reg <= REG_R15: 732 args[1] = C_REG 733 case REG_V0 <= p.Reg && p.Reg <= REG_V31: 734 args[1] = C_VREG 735 case REG_F0 <= p.Reg && p.Reg <= REG_F15: 736 args[1] = C_FREG 737 case REG_AR0 <= p.Reg && p.Reg <= REG_AR15: 738 args[1] = C_AREG 739 } 740 // Fill in argument classes for p.RestArgs. 741 for i, a := range p.RestArgs { 742 args[2+i] = a.Class - 1 743 } 744 745 // Lookup op in optab. 746 ops := oprange[p.As&obj.AMask] 747 cmp := [len(args)]*[C_NCLASS]bool{} 748 for i := range cmp { 749 cmp[i] = &xcmp[args[i]] 750 } 751 for i := range ops { 752 op := &ops[i] 753 if cmp[0][op.a1] && cmp[1][op.a2] && 754 cmp[2][op.a3] && cmp[3][op.a4] && 755 cmp[4][op.a5] && cmp[5][op.a6] { 756 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 757 return op 758 } 759 } 760 761 // Cannot find a case; abort. 762 s := "" 763 for _, a := range args { 764 s += fmt.Sprintf(" %v", DRconv(int(a))) 765 } 766 c.ctxt.Diag("illegal combination %v%v\n", p.As, s) 767 c.ctxt.Diag("prog: %v\n", p) 768 return nil 769 } 770 771 func cmp(a int, b int) bool { 772 if a == b { 773 return true 774 } 775 switch a { 776 case C_DCON: 777 if b == C_LCON { 778 return true 779 } 780 fallthrough 781 case C_LCON: 782 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 783 return true 784 } 785 786 case C_ADDCON: 787 if b == C_ZCON || b == C_SCON { 788 return true 789 } 790 791 case C_ANDCON: 792 if b == C_ZCON || b == C_SCON { 793 return true 794 } 795 796 case C_UCON: 797 if b == C_ZCON || b == C_SCON { 798 return true 799 } 800 801 case C_SCON: 802 if b == C_ZCON { 803 return true 804 } 805 806 case C_LACON: 807 if b == C_SACON { 808 return true 809 } 810 811 case C_LBRA: 812 if b == C_SBRA { 813 return true 814 } 815 816 case C_LAUTO: 817 if b == C_SAUTO { 818 return true 819 } 820 821 case C_LOREG: 822 if b == C_ZOREG || b == C_SOREG { 823 return true 824 } 825 826 case C_SOREG: 827 if b == C_ZOREG { 828 return true 829 } 830 831 case C_ANY: 832 return true 833 } 834 835 return false 836 } 837 838 type ocmp []Optab 839 840 func (x ocmp) Len() int { 841 return len(x) 842 } 843 844 func (x ocmp) Swap(i, j int) { 845 x[i], x[j] = x[j], x[i] 846 } 847 848 func (x ocmp) Less(i, j int) bool { 849 p1 := &x[i] 850 p2 := &x[j] 851 n := int(p1.as) - int(p2.as) 852 if n != 0 { 853 return n < 0 854 } 855 n = int(p1.a1) - int(p2.a1) 856 if n != 0 { 857 return n < 0 858 } 859 n = int(p1.a2) - int(p2.a2) 860 if n != 0 { 861 return n < 0 862 } 863 n = int(p1.a3) - int(p2.a3) 864 if n != 0 { 865 return n < 0 866 } 867 n = int(p1.a4) - int(p2.a4) 868 if n != 0 { 869 return n < 0 870 } 871 return false 872 } 873 func opset(a, b obj.As) { 874 oprange[a&obj.AMask] = oprange[b&obj.AMask] 875 } 876 877 func buildop(ctxt *obj.Link) { 878 if oprange[AORW&obj.AMask] != nil { 879 // Already initialized; stop now. 880 // This happens in the cmd/asm tests, 881 // each of which re-initializes the arch. 882 return 883 } 884 885 for i := 0; i < C_NCLASS; i++ { 886 for n := 0; n < C_NCLASS; n++ { 887 if cmp(n, i) { 888 xcmp[i][n] = true 889 } 890 } 891 } 892 sort.Sort(ocmp(optab)) 893 for i := 0; i < len(optab); i++ { 894 r := optab[i].as 895 start := i 896 for ; i+1 < len(optab); i++ { 897 if optab[i+1].as != r { 898 break 899 } 900 } 901 oprange[r&obj.AMask] = optab[start : i+1] 902 903 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 904 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 905 switch r { 906 case AADD: 907 opset(AADDC, r) 908 opset(AADDW, r) 909 opset(AADDE, r) 910 opset(AMULLD, r) 911 opset(AMULLW, r) 912 case ADIVW: 913 opset(ADIVD, r) 914 opset(ADIVDU, r) 915 opset(ADIVWU, r) 916 opset(AMODD, r) 917 opset(AMODDU, r) 918 opset(AMODW, r) 919 opset(AMODWU, r) 920 case AMULHD: 921 opset(AMULHDU, r) 922 case AMOVBZ: 923 opset(AMOVH, r) 924 opset(AMOVHZ, r) 925 case ALA: 926 opset(ALAY, r) 927 case AMVC: 928 opset(AMVCIN, r) 929 opset(ACLC, r) 930 opset(AXC, r) 931 opset(AOC, r) 932 opset(ANC, r) 933 case ASTCK: 934 opset(ASTCKC, r) 935 opset(ASTCKE, r) 936 opset(ASTCKF, r) 937 case ALAAG: 938 opset(ALAA, r) 939 opset(ALAAL, r) 940 opset(ALAALG, r) 941 opset(ALAN, r) 942 opset(ALANG, r) 943 opset(ALAX, r) 944 opset(ALAXG, r) 945 opset(ALAO, r) 946 opset(ALAOG, r) 947 case ASTMG: 948 opset(ASTMY, r) 949 case ALMG: 950 opset(ALMY, r) 951 case ABEQ: 952 opset(ABGE, r) 953 opset(ABGT, r) 954 opset(ABLE, r) 955 opset(ABLT, r) 956 opset(ABNE, r) 957 opset(ABVC, r) 958 opset(ABVS, r) 959 opset(ABLEU, r) 960 opset(ABLTU, r) 961 case ABR: 962 opset(ABL, r) 963 case ABC: 964 opset(ABCL, r) 965 case AFABS: 966 opset(AFNABS, r) 967 opset(ALPDFR, r) 968 opset(ALNDFR, r) 969 opset(AFNEG, r) 970 opset(AFNEGS, r) 971 opset(ALEDBR, r) 972 opset(ALDEBR, r) 973 opset(AFSQRT, r) 974 opset(AFSQRTS, r) 975 case AFADD: 976 opset(AFADDS, r) 977 opset(AFDIV, r) 978 opset(AFDIVS, r) 979 opset(AFSUB, r) 980 opset(AFSUBS, r) 981 case AFMADD: 982 opset(AFMADDS, r) 983 opset(AFMSUB, r) 984 opset(AFMSUBS, r) 985 case AFMUL: 986 opset(AFMULS, r) 987 case AFCMPO: 988 opset(AFCMPU, r) 989 opset(ACEBR, r) 990 case AAND: 991 opset(AOR, r) 992 opset(AXOR, r) 993 case AANDW: 994 opset(AORW, r) 995 opset(AXORW, r) 996 case ASLD: 997 opset(ASRD, r) 998 opset(ASLW, r) 999 opset(ASRW, r) 1000 opset(ASRAD, r) 1001 opset(ASRAW, r) 1002 opset(ARLL, r) 1003 opset(ARLLG, r) 1004 case ARNSBG: 1005 opset(ARXSBG, r) 1006 opset(AROSBG, r) 1007 opset(ARNSBGT, r) 1008 opset(ARXSBGT, r) 1009 opset(AROSBGT, r) 1010 opset(ARISBG, r) 1011 opset(ARISBGN, r) 1012 opset(ARISBGZ, r) 1013 opset(ARISBGNZ, r) 1014 opset(ARISBHG, r) 1015 opset(ARISBLG, r) 1016 opset(ARISBHGZ, r) 1017 opset(ARISBLGZ, r) 1018 case ACSG: 1019 opset(ACS, r) 1020 case ASUB: 1021 opset(ASUBC, r) 1022 opset(ASUBE, r) 1023 opset(ASUBW, r) 1024 case ANEG: 1025 opset(ANEGW, r) 1026 case AFMOVD: 1027 opset(AFMOVS, r) 1028 case AMOVDBR: 1029 opset(AMOVWBR, r) 1030 case ACMP: 1031 opset(ACMPW, r) 1032 case ACMPU: 1033 opset(ACMPWU, r) 1034 case ATMHH: 1035 opset(ATMHL, r) 1036 opset(ATMLH, r) 1037 opset(ATMLL, r) 1038 case ACEFBRA: 1039 opset(ACDFBRA, r) 1040 opset(ACEGBRA, r) 1041 opset(ACDGBRA, r) 1042 opset(ACELFBR, r) 1043 opset(ACDLFBR, r) 1044 opset(ACELGBR, r) 1045 opset(ACDLGBR, r) 1046 case ACFEBRA: 1047 opset(ACFDBRA, r) 1048 opset(ACGEBRA, r) 1049 opset(ACGDBRA, r) 1050 opset(ACLFEBR, r) 1051 opset(ACLFDBR, r) 1052 opset(ACLGEBR, r) 1053 opset(ACLGDBR, r) 1054 case AFIEBR: 1055 opset(AFIDBR, r) 1056 case ACMPBEQ: 1057 opset(ACMPBGE, r) 1058 opset(ACMPBGT, r) 1059 opset(ACMPBLE, r) 1060 opset(ACMPBLT, r) 1061 opset(ACMPBNE, r) 1062 case ACMPUBEQ: 1063 opset(ACMPUBGE, r) 1064 opset(ACMPUBGT, r) 1065 opset(ACMPUBLE, r) 1066 opset(ACMPUBLT, r) 1067 opset(ACMPUBNE, r) 1068 case ACGRJ: 1069 opset(ACRJ, r) 1070 case ACLGRJ: 1071 opset(ACLRJ, r) 1072 case ACGIJ: 1073 opset(ACIJ, r) 1074 case ACLGIJ: 1075 opset(ACLIJ, r) 1076 case AMOVDEQ: 1077 opset(AMOVDGE, r) 1078 opset(AMOVDGT, r) 1079 opset(AMOVDLE, r) 1080 opset(AMOVDLT, r) 1081 opset(AMOVDNE, r) 1082 case ALOCGR: 1083 opset(ALOCR, r) 1084 case ALTDBR: 1085 opset(ALTEBR, r) 1086 case ATCDB: 1087 opset(ATCEB, r) 1088 case AVL: 1089 opset(AVLLEZB, r) 1090 opset(AVLLEZH, r) 1091 opset(AVLLEZF, r) 1092 opset(AVLLEZG, r) 1093 opset(AVLREPB, r) 1094 opset(AVLREPH, r) 1095 opset(AVLREPF, r) 1096 opset(AVLREPG, r) 1097 case AVLEG: 1098 opset(AVLBB, r) 1099 opset(AVLEB, r) 1100 opset(AVLEH, r) 1101 opset(AVLEF, r) 1102 opset(AVLEG, r) 1103 opset(AVLREP, r) 1104 case AVSTEG: 1105 opset(AVSTEB, r) 1106 opset(AVSTEH, r) 1107 opset(AVSTEF, r) 1108 case AVSCEG: 1109 opset(AVSCEF, r) 1110 case AVGEG: 1111 opset(AVGEF, r) 1112 case AVESLG: 1113 opset(AVESLB, r) 1114 opset(AVESLH, r) 1115 opset(AVESLF, r) 1116 opset(AVERLLB, r) 1117 opset(AVERLLH, r) 1118 opset(AVERLLF, r) 1119 opset(AVERLLG, r) 1120 opset(AVESRAB, r) 1121 opset(AVESRAH, r) 1122 opset(AVESRAF, r) 1123 opset(AVESRAG, r) 1124 opset(AVESRLB, r) 1125 opset(AVESRLH, r) 1126 opset(AVESRLF, r) 1127 opset(AVESRLG, r) 1128 case AVLGVG: 1129 opset(AVLGVB, r) 1130 opset(AVLGVH, r) 1131 opset(AVLGVF, r) 1132 case AVLVGG: 1133 opset(AVLVGB, r) 1134 opset(AVLVGH, r) 1135 opset(AVLVGF, r) 1136 case AVZERO: 1137 opset(AVONE, r) 1138 case AVREPIG: 1139 opset(AVREPIB, r) 1140 opset(AVREPIH, r) 1141 opset(AVREPIF, r) 1142 case AVLEIG: 1143 opset(AVLEIB, r) 1144 opset(AVLEIH, r) 1145 opset(AVLEIF, r) 1146 case AVGMG: 1147 opset(AVGMB, r) 1148 opset(AVGMH, r) 1149 opset(AVGMF, r) 1150 case AVREPG: 1151 opset(AVREPB, r) 1152 opset(AVREPH, r) 1153 opset(AVREPF, r) 1154 case AVERIMG: 1155 opset(AVERIMB, r) 1156 opset(AVERIMH, r) 1157 opset(AVERIMF, r) 1158 case AVFTCIDB: 1159 opset(AWFTCIDB, r) 1160 case AVLR: 1161 opset(AVUPHB, r) 1162 opset(AVUPHH, r) 1163 opset(AVUPHF, r) 1164 opset(AVUPLHB, r) 1165 opset(AVUPLHH, r) 1166 opset(AVUPLHF, r) 1167 opset(AVUPLB, r) 1168 opset(AVUPLHW, r) 1169 opset(AVUPLF, r) 1170 opset(AVUPLLB, r) 1171 opset(AVUPLLH, r) 1172 opset(AVUPLLF, r) 1173 opset(AVCLZB, r) 1174 opset(AVCLZH, r) 1175 opset(AVCLZF, r) 1176 opset(AVCLZG, r) 1177 opset(AVCTZB, r) 1178 opset(AVCTZH, r) 1179 opset(AVCTZF, r) 1180 opset(AVCTZG, r) 1181 opset(AVLDEB, r) 1182 opset(AWLDEB, r) 1183 opset(AVFLCDB, r) 1184 opset(AWFLCDB, r) 1185 opset(AVFLNDB, r) 1186 opset(AWFLNDB, r) 1187 opset(AVFLPDB, r) 1188 opset(AWFLPDB, r) 1189 opset(AVFSQDB, r) 1190 opset(AWFSQDB, r) 1191 opset(AVISTRB, r) 1192 opset(AVISTRH, r) 1193 opset(AVISTRF, r) 1194 opset(AVISTRBS, r) 1195 opset(AVISTRHS, r) 1196 opset(AVISTRFS, r) 1197 opset(AVLCB, r) 1198 opset(AVLCH, r) 1199 opset(AVLCF, r) 1200 opset(AVLCG, r) 1201 opset(AVLPB, r) 1202 opset(AVLPH, r) 1203 opset(AVLPF, r) 1204 opset(AVLPG, r) 1205 opset(AVPOPCT, r) 1206 opset(AVSEGB, r) 1207 opset(AVSEGH, r) 1208 opset(AVSEGF, r) 1209 case AVECG: 1210 opset(AVECB, r) 1211 opset(AVECH, r) 1212 opset(AVECF, r) 1213 opset(AVECLB, r) 1214 opset(AVECLH, r) 1215 opset(AVECLF, r) 1216 opset(AVECLG, r) 1217 opset(AWFCDB, r) 1218 opset(AWFKDB, r) 1219 case AVCEQG: 1220 opset(AVCEQB, r) 1221 opset(AVCEQH, r) 1222 opset(AVCEQF, r) 1223 opset(AVCEQBS, r) 1224 opset(AVCEQHS, r) 1225 opset(AVCEQFS, r) 1226 opset(AVCEQGS, r) 1227 opset(AVCHB, r) 1228 opset(AVCHH, r) 1229 opset(AVCHF, r) 1230 opset(AVCHG, r) 1231 opset(AVCHBS, r) 1232 opset(AVCHHS, r) 1233 opset(AVCHFS, r) 1234 opset(AVCHGS, r) 1235 opset(AVCHLB, r) 1236 opset(AVCHLH, r) 1237 opset(AVCHLF, r) 1238 opset(AVCHLG, r) 1239 opset(AVCHLBS, r) 1240 opset(AVCHLHS, r) 1241 opset(AVCHLFS, r) 1242 opset(AVCHLGS, r) 1243 case AVFAEF: 1244 opset(AVFAEB, r) 1245 opset(AVFAEH, r) 1246 opset(AVFAEBS, r) 1247 opset(AVFAEHS, r) 1248 opset(AVFAEFS, r) 1249 opset(AVFAEZB, r) 1250 opset(AVFAEZH, r) 1251 opset(AVFAEZF, r) 1252 opset(AVFAEZBS, r) 1253 opset(AVFAEZHS, r) 1254 opset(AVFAEZFS, r) 1255 opset(AVFEEB, r) 1256 opset(AVFEEH, r) 1257 opset(AVFEEF, r) 1258 opset(AVFEEBS, r) 1259 opset(AVFEEHS, r) 1260 opset(AVFEEFS, r) 1261 opset(AVFEEZB, r) 1262 opset(AVFEEZH, r) 1263 opset(AVFEEZF, r) 1264 opset(AVFEEZBS, r) 1265 opset(AVFEEZHS, r) 1266 opset(AVFEEZFS, r) 1267 opset(AVFENEB, r) 1268 opset(AVFENEH, r) 1269 opset(AVFENEF, r) 1270 opset(AVFENEBS, r) 1271 opset(AVFENEHS, r) 1272 opset(AVFENEFS, r) 1273 opset(AVFENEZB, r) 1274 opset(AVFENEZH, r) 1275 opset(AVFENEZF, r) 1276 opset(AVFENEZBS, r) 1277 opset(AVFENEZHS, r) 1278 opset(AVFENEZFS, r) 1279 case AVPKSG: 1280 opset(AVPKSH, r) 1281 opset(AVPKSF, r) 1282 opset(AVPKSHS, r) 1283 opset(AVPKSFS, r) 1284 opset(AVPKSGS, r) 1285 opset(AVPKLSH, r) 1286 opset(AVPKLSF, r) 1287 opset(AVPKLSG, r) 1288 opset(AVPKLSHS, r) 1289 opset(AVPKLSFS, r) 1290 opset(AVPKLSGS, r) 1291 case AVAQ: 1292 opset(AVAB, r) 1293 opset(AVAH, r) 1294 opset(AVAF, r) 1295 opset(AVAG, r) 1296 opset(AVACCB, r) 1297 opset(AVACCH, r) 1298 opset(AVACCF, r) 1299 opset(AVACCG, r) 1300 opset(AVACCQ, r) 1301 opset(AVN, r) 1302 opset(AVNC, r) 1303 opset(AVAVGB, r) 1304 opset(AVAVGH, r) 1305 opset(AVAVGF, r) 1306 opset(AVAVGG, r) 1307 opset(AVAVGLB, r) 1308 opset(AVAVGLH, r) 1309 opset(AVAVGLF, r) 1310 opset(AVAVGLG, r) 1311 opset(AVCKSM, r) 1312 opset(AVX, r) 1313 opset(AVFADB, r) 1314 opset(AWFADB, r) 1315 opset(AVFCEDB, r) 1316 opset(AVFCEDBS, r) 1317 opset(AWFCEDB, r) 1318 opset(AWFCEDBS, r) 1319 opset(AVFCHDB, r) 1320 opset(AVFCHDBS, r) 1321 opset(AWFCHDB, r) 1322 opset(AWFCHDBS, r) 1323 opset(AVFCHEDB, r) 1324 opset(AVFCHEDBS, r) 1325 opset(AWFCHEDB, r) 1326 opset(AWFCHEDBS, r) 1327 opset(AVFMDB, r) 1328 opset(AWFMDB, r) 1329 opset(AVGFMB, r) 1330 opset(AVGFMH, r) 1331 opset(AVGFMF, r) 1332 opset(AVGFMG, r) 1333 opset(AVMXB, r) 1334 opset(AVMXH, r) 1335 opset(AVMXF, r) 1336 opset(AVMXG, r) 1337 opset(AVMXLB, r) 1338 opset(AVMXLH, r) 1339 opset(AVMXLF, r) 1340 opset(AVMXLG, r) 1341 opset(AVMNB, r) 1342 opset(AVMNH, r) 1343 opset(AVMNF, r) 1344 opset(AVMNG, r) 1345 opset(AVMNLB, r) 1346 opset(AVMNLH, r) 1347 opset(AVMNLF, r) 1348 opset(AVMNLG, r) 1349 opset(AVMRHB, r) 1350 opset(AVMRHH, r) 1351 opset(AVMRHF, r) 1352 opset(AVMRHG, r) 1353 opset(AVMRLB, r) 1354 opset(AVMRLH, r) 1355 opset(AVMRLF, r) 1356 opset(AVMRLG, r) 1357 opset(AVMEB, r) 1358 opset(AVMEH, r) 1359 opset(AVMEF, r) 1360 opset(AVMLEB, r) 1361 opset(AVMLEH, r) 1362 opset(AVMLEF, r) 1363 opset(AVMOB, r) 1364 opset(AVMOH, r) 1365 opset(AVMOF, r) 1366 opset(AVMLOB, r) 1367 opset(AVMLOH, r) 1368 opset(AVMLOF, r) 1369 opset(AVMHB, r) 1370 opset(AVMHH, r) 1371 opset(AVMHF, r) 1372 opset(AVMLHB, r) 1373 opset(AVMLHH, r) 1374 opset(AVMLHF, r) 1375 opset(AVMLH, r) 1376 opset(AVMLHW, r) 1377 opset(AVMLF, r) 1378 opset(AVNO, r) 1379 opset(AVO, r) 1380 opset(AVPKH, r) 1381 opset(AVPKF, r) 1382 opset(AVPKG, r) 1383 opset(AVSUMGH, r) 1384 opset(AVSUMGF, r) 1385 opset(AVSUMQF, r) 1386 opset(AVSUMQG, r) 1387 opset(AVSUMB, r) 1388 opset(AVSUMH, r) 1389 case AVERLLVG: 1390 opset(AVERLLVB, r) 1391 opset(AVERLLVH, r) 1392 opset(AVERLLVF, r) 1393 opset(AVESLVB, r) 1394 opset(AVESLVH, r) 1395 opset(AVESLVF, r) 1396 opset(AVESLVG, r) 1397 opset(AVESRAVB, r) 1398 opset(AVESRAVH, r) 1399 opset(AVESRAVF, r) 1400 opset(AVESRAVG, r) 1401 opset(AVESRLVB, r) 1402 opset(AVESRLVH, r) 1403 opset(AVESRLVF, r) 1404 opset(AVESRLVG, r) 1405 opset(AVFDDB, r) 1406 opset(AWFDDB, r) 1407 opset(AVFSDB, r) 1408 opset(AWFSDB, r) 1409 opset(AVSL, r) 1410 opset(AVSLB, r) 1411 opset(AVSRA, r) 1412 opset(AVSRAB, r) 1413 opset(AVSRL, r) 1414 opset(AVSRLB, r) 1415 opset(AVSB, r) 1416 opset(AVSH, r) 1417 opset(AVSF, r) 1418 opset(AVSG, r) 1419 opset(AVSQ, r) 1420 opset(AVSCBIB, r) 1421 opset(AVSCBIH, r) 1422 opset(AVSCBIF, r) 1423 opset(AVSCBIG, r) 1424 opset(AVSCBIQ, r) 1425 case AVACQ: 1426 opset(AVACCCQ, r) 1427 opset(AVGFMAB, r) 1428 opset(AVGFMAH, r) 1429 opset(AVGFMAF, r) 1430 opset(AVGFMAG, r) 1431 opset(AVMALB, r) 1432 opset(AVMALHW, r) 1433 opset(AVMALF, r) 1434 opset(AVMAHB, r) 1435 opset(AVMAHH, r) 1436 opset(AVMAHF, r) 1437 opset(AVMALHB, r) 1438 opset(AVMALHH, r) 1439 opset(AVMALHF, r) 1440 opset(AVMAEB, r) 1441 opset(AVMAEH, r) 1442 opset(AVMAEF, r) 1443 opset(AVMALEB, r) 1444 opset(AVMALEH, r) 1445 opset(AVMALEF, r) 1446 opset(AVMAOB, r) 1447 opset(AVMAOH, r) 1448 opset(AVMAOF, r) 1449 opset(AVMALOB, r) 1450 opset(AVMALOH, r) 1451 opset(AVMALOF, r) 1452 opset(AVSTRCB, r) 1453 opset(AVSTRCH, r) 1454 opset(AVSTRCF, r) 1455 opset(AVSTRCBS, r) 1456 opset(AVSTRCHS, r) 1457 opset(AVSTRCFS, r) 1458 opset(AVSTRCZB, r) 1459 opset(AVSTRCZH, r) 1460 opset(AVSTRCZF, r) 1461 opset(AVSTRCZBS, r) 1462 opset(AVSTRCZHS, r) 1463 opset(AVSTRCZFS, r) 1464 opset(AVSBCBIQ, r) 1465 opset(AVSBIQ, r) 1466 opset(AVMSLG, r) 1467 opset(AVMSLEG, r) 1468 opset(AVMSLOG, r) 1469 opset(AVMSLEOG, r) 1470 case AVSEL: 1471 opset(AVFMADB, r) 1472 opset(AWFMADB, r) 1473 opset(AVFMSDB, r) 1474 opset(AWFMSDB, r) 1475 opset(AVPERM, r) 1476 } 1477 } 1478 } 1479 1480 const ( 1481 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1482 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1483 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1484 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1485 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1486 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1487 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1488 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1489 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1490 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1491 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1492 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1493 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1494 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1495 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1496 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1497 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1498 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1499 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1500 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1501 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1502 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1503 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1504 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1505 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1506 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1507 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1508 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1509 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1510 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1511 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1512 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1513 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1514 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1515 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1516 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1517 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1518 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1519 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1520 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1521 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1522 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1523 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1524 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1525 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1526 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1527 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1528 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1529 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1530 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1531 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1532 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1533 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1534 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1535 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1536 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1537 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1538 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1539 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1540 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1541 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1542 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1543 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1544 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1545 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1546 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1547 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1548 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1549 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1550 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1551 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1552 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1553 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1554 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1555 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1556 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1557 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1558 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1559 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1560 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1561 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1562 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1563 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1564 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1565 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1566 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1567 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1568 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1569 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1570 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1571 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1572 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1573 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1574 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1575 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1576 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1577 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1578 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1579 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1580 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1581 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1582 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1583 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1584 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1585 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1586 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1587 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1588 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1589 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1590 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1591 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1592 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1593 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1594 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1595 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1596 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1597 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1598 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1599 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1600 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1601 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1602 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1603 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1604 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1605 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1606 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1607 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1608 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1609 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1610 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1611 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1612 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1613 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1614 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1615 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1616 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1617 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1618 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1619 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1620 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1621 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1622 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1623 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1624 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1625 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1626 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1627 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1628 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1629 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1630 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1631 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1632 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1633 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1634 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1635 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1636 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1637 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1638 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1639 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1640 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1641 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1642 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1643 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1644 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1645 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1646 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1647 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1648 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1649 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1650 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1651 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1652 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1653 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1654 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1655 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1656 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1657 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1658 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1659 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1660 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1661 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1662 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1663 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1664 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1665 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1666 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1667 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1668 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1669 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1670 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1671 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1672 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1673 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1674 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1675 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1676 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1677 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1678 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1679 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1680 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1681 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1682 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1683 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1684 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1685 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1686 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1687 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1688 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1689 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1690 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1691 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1692 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1693 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1694 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1695 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1696 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1697 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1698 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1699 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1700 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1701 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1702 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1703 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1704 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1705 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1706 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1707 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1708 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1709 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1710 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1711 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1712 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1713 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1714 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1715 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1716 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1717 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1718 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1719 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1720 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1721 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1722 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1723 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1724 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1725 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1726 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1727 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1728 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1729 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1730 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1731 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1732 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1733 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1734 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1735 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1736 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1737 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1738 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1739 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1740 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1741 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1742 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1743 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1744 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1745 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1746 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1747 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1748 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1749 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1750 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1751 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1752 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1753 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1754 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1755 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1756 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1757 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1758 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1759 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1760 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1761 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1762 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1763 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1764 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1765 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1766 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1767 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1768 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1769 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1770 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1771 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1772 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1773 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1774 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1775 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1776 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1777 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1778 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1779 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1780 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1781 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1782 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1783 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1784 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1785 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1786 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1787 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1788 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1789 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1790 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1791 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1792 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1793 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1794 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1795 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1796 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1797 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1798 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1799 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1800 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1801 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1802 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1803 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1804 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1805 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1806 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1807 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1808 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1809 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1810 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1811 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1812 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1813 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1814 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1815 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1816 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1817 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1818 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1819 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1820 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1821 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1822 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1823 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1824 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1825 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1826 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1827 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1828 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1829 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1830 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1831 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1832 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1833 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1834 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1835 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1836 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1837 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1838 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1839 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1840 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1841 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1842 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1843 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1844 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1845 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1846 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1847 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1848 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1849 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1850 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1851 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1852 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1853 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1854 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1855 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1856 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1857 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1858 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1859 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1860 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1861 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1862 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1863 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1864 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1865 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1866 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1867 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1868 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1869 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1870 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1871 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1872 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1873 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1874 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1875 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1876 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1877 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1878 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1879 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1880 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1881 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1882 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1883 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1884 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1885 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1886 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1887 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1888 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1889 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1890 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1891 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1892 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1893 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1894 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1895 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1896 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1897 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1898 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1899 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1900 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1901 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1902 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1903 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1904 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1905 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1906 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1907 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1908 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1909 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1910 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1911 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1912 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1913 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1914 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1915 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1916 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1917 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1918 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1919 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1920 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1921 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1922 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1923 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1924 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1925 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1926 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1927 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1928 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1929 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1930 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1931 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1932 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1933 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1934 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1935 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1936 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1937 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1938 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1939 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1940 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1941 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1942 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1943 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1944 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1945 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1946 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1947 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1948 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1949 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1950 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1951 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1952 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1953 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1954 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1955 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1956 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1957 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1958 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1959 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1960 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1961 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1962 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1963 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1964 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1965 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1966 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1967 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1968 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1969 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1970 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1971 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1972 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1973 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1974 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 1975 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 1976 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 1977 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 1978 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 1979 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 1980 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 1981 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 1982 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 1983 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 1984 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 1985 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 1986 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 1987 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 1988 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 1989 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 1990 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 1991 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 1992 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 1993 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 1994 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 1995 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 1996 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 1997 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 1998 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 1999 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 2000 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 2001 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 2002 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 2003 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 2004 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 2005 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 2006 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 2007 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 2008 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 2009 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 2010 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 2011 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 2012 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 2013 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 2014 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 2015 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 2016 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 2017 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 2018 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 2019 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 2020 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 2021 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 2022 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 2023 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 2024 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 2025 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 2026 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 2027 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 2028 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 2029 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 2030 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 2031 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 2032 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 2033 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 2034 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 2035 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 2036 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 2037 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 2038 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 2039 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 2040 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 2041 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 2042 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 2043 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 2044 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 2045 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 2046 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 2047 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 2048 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 2049 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 2050 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 2051 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 2052 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 2053 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 2054 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 2055 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 2056 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 2057 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 2058 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 2059 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 2060 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 2061 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 2062 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 2063 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 2064 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 2065 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 2066 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 2067 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 2068 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 2069 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 2070 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 2071 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 2072 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 2073 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 2074 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 2075 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 2076 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 2077 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 2078 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 2079 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 2080 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 2081 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 2082 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 2083 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 2084 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 2085 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 2086 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 2087 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 2088 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 2089 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 2090 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 2091 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 2092 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 2093 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 2094 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 2095 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 2096 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 2097 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 2098 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 2099 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 2100 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 2101 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 2102 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 2103 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 2104 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 2105 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 2106 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 2107 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 2108 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 2109 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 2110 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 2111 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 2112 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 2113 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 2114 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 2115 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 2116 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 2117 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 2118 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 2119 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 2120 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 2121 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 2122 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 2123 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 2124 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 2125 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 2126 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 2127 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 2128 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 2129 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 2130 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 2131 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 2132 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 2133 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 2134 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 2135 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 2136 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 2137 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 2138 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 2139 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 2140 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 2141 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 2142 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 2143 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 2144 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 2145 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 2146 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 2147 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 2148 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 2149 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 2150 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 2151 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 2152 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 2153 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 2154 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 2155 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 2156 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 2157 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 2158 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 2159 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2160 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2161 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 2162 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 2163 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2164 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2165 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2166 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2167 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2168 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2169 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2170 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2171 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2172 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2173 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2174 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2175 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2176 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2177 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2178 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2179 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2180 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2181 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2182 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2183 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2184 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2185 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2186 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2187 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2188 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2189 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2190 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2191 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2192 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2193 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2194 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2195 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2196 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2197 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2198 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2199 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2200 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2201 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2202 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2203 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2204 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2205 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2206 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2207 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2208 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2209 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2210 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2211 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2212 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2213 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2214 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2215 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2216 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2217 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2218 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2219 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2220 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2221 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2222 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2223 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2224 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2225 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2226 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2227 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2228 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2229 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2230 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2231 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2232 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2233 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2234 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2235 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2236 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2237 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2238 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2239 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2240 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2241 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2242 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2243 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2244 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2245 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2246 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2247 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2248 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2249 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2250 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2251 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2252 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2253 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2254 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2255 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2256 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2257 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2258 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2259 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2260 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2261 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2262 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2263 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2264 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2265 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2266 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2267 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2268 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2269 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2270 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2271 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2272 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2273 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2274 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2275 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2276 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2277 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2278 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2279 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2280 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2281 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2282 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2283 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2284 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2285 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2286 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2287 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2288 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2289 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2290 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2291 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2292 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2293 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2294 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2295 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2296 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2297 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2298 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2299 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2300 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2301 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2302 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2303 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2304 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2305 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2306 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2307 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2308 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2309 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2310 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2311 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2312 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2313 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2314 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2315 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2316 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2317 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2318 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2319 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2320 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2321 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2322 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2323 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2324 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2325 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2326 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2327 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2328 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2329 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2330 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2331 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2332 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2333 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2334 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2335 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2336 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2337 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2338 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2339 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2340 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2341 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2342 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2343 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2344 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2345 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2346 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2347 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2348 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2349 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2350 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2351 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2352 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2353 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2354 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2355 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2356 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2357 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2358 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2359 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2360 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2361 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2362 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2363 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2364 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2365 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2366 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2367 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2368 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2369 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2370 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2371 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2372 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2373 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2374 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2375 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2376 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2377 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2378 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2379 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2380 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2381 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2382 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2383 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2384 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2385 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2386 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2387 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2388 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2389 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2390 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2391 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2392 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2393 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2394 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2395 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2396 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2397 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2398 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2399 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2400 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2401 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2402 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2403 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2404 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2405 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2406 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2407 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2408 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2409 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2410 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2411 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2412 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2413 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2414 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2415 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2416 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2417 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2418 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2419 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2420 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2421 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2422 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2423 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2424 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2425 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2426 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2427 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2428 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2429 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2430 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2431 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2432 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2433 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2434 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2435 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2436 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2437 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2438 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2439 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2440 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2441 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2442 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2443 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2444 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2445 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2446 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2447 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2448 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2449 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2450 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2451 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2452 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2453 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2454 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2455 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2456 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2457 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2458 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2459 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2460 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2461 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2462 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2463 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2464 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2465 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2466 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2467 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2468 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2469 2470 // added in z13 2471 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2472 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2473 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2474 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2475 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2476 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2477 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2478 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2479 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2480 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2481 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2482 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2483 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2484 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2485 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2486 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2487 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2488 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2489 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2490 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2491 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2492 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2493 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2494 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2495 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2496 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2497 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2498 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2499 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2500 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2501 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2502 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2503 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2504 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2505 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2506 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2507 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2508 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2509 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2510 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2511 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2512 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2513 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2514 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2515 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2516 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2517 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2518 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2519 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2520 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2521 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2522 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2523 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2524 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2525 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2526 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2527 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2528 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2529 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2530 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2531 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2532 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2533 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2534 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2535 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2536 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2537 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2538 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2539 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2540 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2541 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2542 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2543 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2544 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2545 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2546 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2547 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2548 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2549 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2550 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2551 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2552 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2553 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2554 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2555 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2556 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2557 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2558 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2559 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2560 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2561 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2562 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2563 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2564 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2565 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2566 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2567 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2568 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2569 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2570 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2571 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2572 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2573 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2574 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2575 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2576 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2577 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2578 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2579 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2580 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2581 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2582 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2583 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2584 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2585 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2586 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2587 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2588 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2589 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2590 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2591 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2592 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2593 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2594 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2595 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2596 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2597 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2598 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2599 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2600 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2601 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2602 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2603 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2604 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2605 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2606 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2607 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2608 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2609 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2610 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2611 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2612 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2613 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2614 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2615 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2616 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2617 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2618 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2619 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2620 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2621 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2622 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2623 op_VMSL uint32 = 0xE7B8 // VRR-d VECTOR MULTIPLY SUM LOGICAL 2624 ) 2625 2626 func oclass(a *obj.Addr) int { 2627 return int(a.Class) - 1 2628 } 2629 2630 // Add a relocation for the immediate in a RIL style instruction. 2631 // The addend will be adjusted as required. 2632 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) *obj.Reloc { 2633 if sym == nil { 2634 c.ctxt.Diag("require symbol to apply relocation") 2635 } 2636 offset := int64(2) // relocation offset from start of instruction 2637 rel := obj.Addrel(c.cursym) 2638 rel.Off = int32(c.pc + offset) 2639 rel.Siz = 4 2640 rel.Sym = sym 2641 rel.Add = add + offset + int64(rel.Siz) 2642 rel.Type = objabi.R_PCRELDBL 2643 return rel 2644 } 2645 2646 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) *obj.Reloc { 2647 if sym == nil { 2648 c.ctxt.Diag("require symbol to apply relocation") 2649 } 2650 offset += int64(2) // relocation offset from start of instruction 2651 rel := obj.Addrel(c.cursym) 2652 rel.Off = int32(c.pc + offset) 2653 rel.Siz = 4 2654 rel.Sym = sym 2655 rel.Add = add + offset + int64(rel.Siz) 2656 rel.Type = objabi.R_PCRELDBL 2657 return rel 2658 } 2659 2660 // Add a CALL relocation for the immediate in a RIL style instruction. 2661 // The addend will be adjusted as required. 2662 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) *obj.Reloc { 2663 if sym == nil { 2664 c.ctxt.Diag("require symbol to apply relocation") 2665 } 2666 offset := int64(2) // relocation offset from start of instruction 2667 rel := obj.Addrel(c.cursym) 2668 rel.Off = int32(c.pc + offset) 2669 rel.Siz = 4 2670 rel.Sym = sym 2671 rel.Add = add + offset + int64(rel.Siz) 2672 rel.Type = objabi.R_CALL 2673 return rel 2674 } 2675 2676 func (c *ctxtz) branchMask(p *obj.Prog) CCMask { 2677 switch p.As { 2678 case ABRC, ALOCR, ALOCGR, 2679 ACRJ, ACGRJ, ACIJ, ACGIJ, 2680 ACLRJ, ACLGRJ, ACLIJ, ACLGIJ: 2681 return CCMask(p.From.Offset) 2682 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ: 2683 return Equal 2684 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE: 2685 return GreaterOrEqual 2686 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT: 2687 return Greater 2688 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE: 2689 return LessOrEqual 2690 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT: 2691 return Less 2692 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE: 2693 return NotEqual 2694 case ABLEU: // LE or unordered 2695 return NotGreater 2696 case ABLTU: // LT or unordered 2697 return LessOrUnordered 2698 case ABVC: 2699 return Never // needs extra instruction 2700 case ABVS: 2701 return Unordered 2702 } 2703 c.ctxt.Diag("unknown conditional branch %v", p.As) 2704 return Always 2705 } 2706 2707 func regtmp(p *obj.Prog) uint32 { 2708 p.Mark |= USETMP 2709 return REGTMP 2710 } 2711 2712 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) { 2713 o := c.oplook(p) 2714 2715 if o == nil { 2716 return 2717 } 2718 2719 // If REGTMP is used in generated code, we need to set USETMP on p.Mark. 2720 // So we use regtmp(p) for REGTMP. 2721 2722 switch o.i { 2723 default: 2724 c.ctxt.Diag("unknown index %d", o.i) 2725 2726 case 0: // PSEUDO OPS 2727 break 2728 2729 case 1: // mov reg reg 2730 switch p.As { 2731 default: 2732 c.ctxt.Diag("unhandled operation: %v", p.As) 2733 case AMOVD: 2734 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2735 // sign extend 2736 case AMOVW: 2737 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2738 case AMOVH: 2739 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2740 case AMOVB: 2741 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2742 // zero extend 2743 case AMOVWZ: 2744 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2745 case AMOVHZ: 2746 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2747 case AMOVBZ: 2748 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2749 // reverse bytes 2750 case AMOVDBR: 2751 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2752 case AMOVWBR: 2753 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2754 // floating point 2755 case AFMOVD, AFMOVS: 2756 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2757 } 2758 2759 case 2: // arithmetic op reg [reg] reg 2760 r := p.Reg 2761 if r == 0 { 2762 r = p.To.Reg 2763 } 2764 2765 var opcode uint32 2766 2767 switch p.As { 2768 default: 2769 c.ctxt.Diag("invalid opcode") 2770 case AADD: 2771 opcode = op_AGRK 2772 case AADDC: 2773 opcode = op_ALGRK 2774 case AADDE: 2775 opcode = op_ALCGR 2776 case AADDW: 2777 opcode = op_ARK 2778 case AMULLW: 2779 opcode = op_MSGFR 2780 case AMULLD: 2781 opcode = op_MSGR 2782 case ADIVW, AMODW: 2783 opcode = op_DSGFR 2784 case ADIVWU, AMODWU: 2785 opcode = op_DLR 2786 case ADIVD, AMODD: 2787 opcode = op_DSGR 2788 case ADIVDU, AMODDU: 2789 opcode = op_DLGR 2790 } 2791 2792 switch p.As { 2793 default: 2794 2795 case AADD, AADDC, AADDW: 2796 if p.As == AADDW && r == p.To.Reg { 2797 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2798 } else { 2799 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2800 } 2801 2802 case AADDE, AMULLW, AMULLD: 2803 if r == p.To.Reg { 2804 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2805 } else if p.From.Reg == p.To.Reg { 2806 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2807 } else { 2808 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2809 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2810 } 2811 2812 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2813 if p.As == ADIVWU || p.As == ADIVDU { 2814 zRI(op_LGHI, regtmp(p), 0, asm) 2815 } 2816 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2817 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm) 2818 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2819 2820 case AMODW, AMODWU, AMODD, AMODDU: 2821 if p.As == AMODWU || p.As == AMODDU { 2822 zRI(op_LGHI, regtmp(p), 0, asm) 2823 } 2824 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2825 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm) 2826 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm) 2827 2828 } 2829 2830 case 3: // mov $constant reg 2831 v := c.vregoff(&p.From) 2832 switch p.As { 2833 case AMOVBZ: 2834 v = int64(uint8(v)) 2835 case AMOVHZ: 2836 v = int64(uint16(v)) 2837 case AMOVWZ: 2838 v = int64(uint32(v)) 2839 case AMOVB: 2840 v = int64(int8(v)) 2841 case AMOVH: 2842 v = int64(int16(v)) 2843 case AMOVW: 2844 v = int64(int32(v)) 2845 } 2846 if int64(int16(v)) == v { 2847 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2848 } else if v&0xffff0000 == v { 2849 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2850 } else if v&0xffff00000000 == v { 2851 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2852 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2853 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2854 } else if int64(int32(v)) == v { 2855 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2856 } else if int64(uint32(v)) == v { 2857 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2858 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2859 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2860 } else { 2861 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2862 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2863 } 2864 2865 case 4: // multiply high (a*b)>>64 2866 r := p.Reg 2867 if r == 0 { 2868 r = p.To.Reg 2869 } 2870 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2871 zRRE(op_MLGR, regtmp(p), uint32(p.From.Reg), asm) 2872 switch p.As { 2873 case AMULHDU: 2874 // Unsigned: move result into correct register. 2875 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm) 2876 case AMULHD: 2877 // Signed: need to convert result. 2878 // See Hacker's Delight 8-3. 2879 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2880 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2881 zRRE(op_SGR, regtmp(p), REGTMP2, asm) 2882 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2883 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2884 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), regtmp(p), asm) 2885 } 2886 2887 case 5: // syscall 2888 zI(op_SVC, 0, asm) 2889 2890 case 6: // logical op reg [reg] reg 2891 var oprr, oprre, oprrf uint32 2892 switch p.As { 2893 case AAND: 2894 oprre = op_NGR 2895 oprrf = op_NGRK 2896 case AANDW: 2897 oprr = op_NR 2898 oprrf = op_NRK 2899 case AOR: 2900 oprre = op_OGR 2901 oprrf = op_OGRK 2902 case AORW: 2903 oprr = op_OR 2904 oprrf = op_ORK 2905 case AXOR: 2906 oprre = op_XGR 2907 oprrf = op_XGRK 2908 case AXORW: 2909 oprr = op_XR 2910 oprrf = op_XRK 2911 } 2912 if p.Reg == 0 { 2913 if oprr != 0 { 2914 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2915 } else { 2916 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2917 } 2918 } else { 2919 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2920 } 2921 2922 case 7: // shift/rotate reg [reg] reg 2923 d2 := c.vregoff(&p.From) 2924 b2 := p.From.Reg 2925 r3 := p.Reg 2926 if r3 == 0 { 2927 r3 = p.To.Reg 2928 } 2929 r1 := p.To.Reg 2930 var opcode uint32 2931 switch p.As { 2932 default: 2933 case ASLD: 2934 opcode = op_SLLG 2935 case ASRD: 2936 opcode = op_SRLG 2937 case ASLW: 2938 opcode = op_SLLK 2939 case ASRW: 2940 opcode = op_SRLK 2941 case ARLL: 2942 opcode = op_RLL 2943 case ARLLG: 2944 opcode = op_RLLG 2945 case ASRAW: 2946 opcode = op_SRAK 2947 case ASRAD: 2948 opcode = op_SRAG 2949 } 2950 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2951 2952 case 8: // find leftmost one 2953 if p.To.Reg&1 != 0 { 2954 c.ctxt.Diag("target must be an even-numbered register") 2955 } 2956 // FLOGR also writes a mask to p.To.Reg+1. 2957 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2958 2959 case 9: // population count 2960 zRRE(op_POPCNT, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2961 2962 case 10: // subtract reg [reg] reg 2963 r := int(p.Reg) 2964 2965 switch p.As { 2966 default: 2967 case ASUB: 2968 if r == 0 { 2969 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2970 } else { 2971 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2972 } 2973 case ASUBC: 2974 if r == 0 { 2975 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2976 } else { 2977 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2978 } 2979 case ASUBE: 2980 if r == 0 { 2981 r = int(p.To.Reg) 2982 } 2983 if r == int(p.To.Reg) { 2984 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2985 } else if p.From.Reg == p.To.Reg { 2986 zRRE(op_LGR, regtmp(p), uint32(p.From.Reg), asm) 2987 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2988 zRRE(op_SLBGR, uint32(p.To.Reg), regtmp(p), asm) 2989 } else { 2990 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2991 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2992 } 2993 case ASUBW: 2994 if r == 0 { 2995 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2996 } else { 2997 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2998 } 2999 } 3000 3001 case 11: // br/bl 3002 v := int32(0) 3003 3004 if p.To.Target() != nil { 3005 v = int32((p.To.Target().Pc - p.Pc) >> 1) 3006 } 3007 3008 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 3009 zRI(op_BRC, 0xF, uint32(v), asm) 3010 } else { 3011 if p.As == ABL { 3012 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 3013 } else { 3014 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 3015 } 3016 if p.To.Sym != nil { 3017 c.addcallreloc(p.To.Sym, p.To.Offset) 3018 } 3019 } 3020 3021 case 12: 3022 r1 := p.To.Reg 3023 d2 := c.vregoff(&p.From) 3024 b2 := p.From.Reg 3025 if b2 == 0 { 3026 b2 = REGSP 3027 } 3028 x2 := p.From.Index 3029 if -DISP20/2 > d2 || d2 >= DISP20/2 { 3030 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm) 3031 if x2 != 0 { 3032 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm) 3033 } 3034 x2 = int16(regtmp(p)) 3035 d2 = 0 3036 } 3037 var opx, opxy uint32 3038 switch p.As { 3039 case AADD: 3040 opxy = op_AG 3041 case AADDC: 3042 opxy = op_ALG 3043 case AADDE: 3044 opxy = op_ALCG 3045 case AADDW: 3046 opx = op_A 3047 opxy = op_AY 3048 case AMULLW: 3049 opx = op_MS 3050 opxy = op_MSY 3051 case AMULLD: 3052 opxy = op_MSG 3053 case ASUB: 3054 opxy = op_SG 3055 case ASUBC: 3056 opxy = op_SLG 3057 case ASUBE: 3058 opxy = op_SLBG 3059 case ASUBW: 3060 opx = op_S 3061 opxy = op_SY 3062 case AAND: 3063 opxy = op_NG 3064 case AANDW: 3065 opx = op_N 3066 opxy = op_NY 3067 case AOR: 3068 opxy = op_OG 3069 case AORW: 3070 opx = op_O 3071 opxy = op_OY 3072 case AXOR: 3073 opxy = op_XG 3074 case AXORW: 3075 opx = op_X 3076 opxy = op_XY 3077 } 3078 if opx != 0 && 0 <= d2 && d2 < DISP12 { 3079 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 3080 } else { 3081 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 3082 } 3083 3084 case 13: // rotate, followed by operation 3085 r1 := p.To.Reg 3086 r2 := p.RestArgs[2].Reg 3087 i3 := uint8(p.From.Offset) // start 3088 i4 := uint8(p.RestArgs[0].Offset) // end 3089 i5 := uint8(p.RestArgs[1].Offset) // rotate amount 3090 switch p.As { 3091 case ARNSBGT, ARXSBGT, AROSBGT: 3092 i3 |= 0x80 // test-results 3093 case ARISBGZ, ARISBGNZ, ARISBHGZ, ARISBLGZ: 3094 i4 |= 0x80 // zero-remaining-bits 3095 } 3096 var opcode uint32 3097 switch p.As { 3098 case ARNSBG, ARNSBGT: 3099 opcode = op_RNSBG 3100 case ARXSBG, ARXSBGT: 3101 opcode = op_RXSBG 3102 case AROSBG, AROSBGT: 3103 opcode = op_ROSBG 3104 case ARISBG, ARISBGZ: 3105 opcode = op_RISBG 3106 case ARISBGN, ARISBGNZ: 3107 opcode = op_RISBGN 3108 case ARISBHG, ARISBHGZ: 3109 opcode = op_RISBHG 3110 case ARISBLG, ARISBLGZ: 3111 opcode = op_RISBLG 3112 } 3113 zRIE(_f, uint32(opcode), uint32(r1), uint32(r2), 0, uint32(i3), uint32(i4), 0, uint32(i5), asm) 3114 3115 case 15: // br/bl (reg) 3116 r := p.To.Reg 3117 if p.As == ABCL || p.As == ABL { 3118 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 3119 } else { 3120 zRR(op_BCR, uint32(Always), uint32(r), asm) 3121 } 3122 3123 case 16: // conditional branch 3124 v := int32(0) 3125 if p.To.Target() != nil { 3126 v = int32((p.To.Target().Pc - p.Pc) >> 1) 3127 } 3128 mask := uint32(c.branchMask(p)) 3129 if p.To.Sym == nil && int32(int16(v)) == v { 3130 zRI(op_BRC, mask, uint32(v), asm) 3131 } else { 3132 zRIL(_c, op_BRCL, mask, uint32(v), asm) 3133 } 3134 if p.To.Sym != nil { 3135 c.addrilreloc(p.To.Sym, p.To.Offset) 3136 } 3137 3138 case 17: // move on condition 3139 m3 := uint32(c.branchMask(p)) 3140 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3141 3142 case 18: // br/bl reg 3143 if p.As == ABL { 3144 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 3145 } else { 3146 zRR(op_BCR, uint32(Always), uint32(p.To.Reg), asm) 3147 } 3148 3149 case 19: // mov $sym+n(SB) reg 3150 d := c.vregoff(&p.From) 3151 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 3152 if d&1 != 0 { 3153 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 3154 d -= 1 3155 } 3156 c.addrilreloc(p.From.Sym, d) 3157 3158 case 21: // subtract $constant [reg] reg 3159 v := c.vregoff(&p.From) 3160 r := p.Reg 3161 if r == 0 { 3162 r = p.To.Reg 3163 } 3164 switch p.As { 3165 case ASUB: 3166 zRIL(_a, op_LGFI, uint32(regtmp(p)), uint32(v), asm) 3167 zRRF(op_SLGRK, uint32(regtmp(p)), 0, uint32(p.To.Reg), uint32(r), asm) 3168 case ASUBC: 3169 if r != p.To.Reg { 3170 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3171 } 3172 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm) 3173 case ASUBW: 3174 if r != p.To.Reg { 3175 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3176 } 3177 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm) 3178 } 3179 3180 case 22: // add/multiply $constant [reg] reg 3181 v := c.vregoff(&p.From) 3182 r := p.Reg 3183 if r == 0 { 3184 r = p.To.Reg 3185 } 3186 var opri, opril, oprie uint32 3187 switch p.As { 3188 case AADD: 3189 opri = op_AGHI 3190 opril = op_AGFI 3191 oprie = op_AGHIK 3192 case AADDC: 3193 opril = op_ALGFI 3194 oprie = op_ALGHSIK 3195 case AADDW: 3196 opri = op_AHI 3197 opril = op_AFI 3198 oprie = op_AHIK 3199 case AMULLW: 3200 opri = op_MHI 3201 opril = op_MSFI 3202 case AMULLD: 3203 opri = op_MGHI 3204 opril = op_MSGFI 3205 } 3206 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) { 3207 switch p.As { 3208 case AADD, AADDC, AMULLD: 3209 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3210 case AADDW, AMULLW: 3211 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3212 } 3213 r = p.To.Reg 3214 } 3215 if opri != 0 && r == p.To.Reg && int64(int16(v)) == v { 3216 zRI(opri, uint32(p.To.Reg), uint32(v), asm) 3217 } else if oprie != 0 && int64(int16(v)) == v { 3218 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 3219 } else { 3220 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm) 3221 } 3222 3223 case 23: // 64-bit logical op $constant reg 3224 // TODO(mundaym): merge with case 24. 3225 v := c.vregoff(&p.From) 3226 switch p.As { 3227 default: 3228 c.ctxt.Diag("%v is not supported", p) 3229 case AAND: 3230 if v >= 0 { // needs zero extend 3231 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3232 zRRE(op_NGR, uint32(p.To.Reg), regtmp(p), asm) 3233 } else if int64(int16(v)) == v { 3234 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3235 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 3236 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3237 } 3238 case AOR: 3239 if int64(uint32(v)) != v { // needs sign extend 3240 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3241 zRRE(op_OGR, uint32(p.To.Reg), regtmp(p), asm) 3242 } else if int64(uint16(v)) == v { 3243 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3244 } else { 3245 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3246 } 3247 case AXOR: 3248 if int64(uint32(v)) != v { // needs sign extend 3249 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3250 zRRE(op_XGR, uint32(p.To.Reg), regtmp(p), asm) 3251 } else { 3252 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3253 } 3254 } 3255 3256 case 24: // 32-bit logical op $constant reg 3257 v := c.vregoff(&p.From) 3258 switch p.As { 3259 case AANDW: 3260 if uint32(v&0xffff0000) == 0xffff0000 { 3261 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3262 } else if uint32(v&0x0000ffff) == 0x0000ffff { 3263 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3264 } else { 3265 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3266 } 3267 case AORW: 3268 if uint32(v&0xffff0000) == 0 { 3269 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3270 } else if uint32(v&0x0000ffff) == 0 { 3271 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3272 } else { 3273 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3274 } 3275 case AXORW: 3276 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3277 } 3278 3279 case 25: // load on condition (register) 3280 m3 := uint32(c.branchMask(p)) 3281 var opcode uint32 3282 switch p.As { 3283 case ALOCR: 3284 opcode = op_LOCR 3285 case ALOCGR: 3286 opcode = op_LOCGR 3287 } 3288 zRRF(opcode, m3, 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3289 3290 case 26: // MOVD $offset(base)(index), reg 3291 v := c.regoff(&p.From) 3292 r := p.From.Reg 3293 if r == 0 { 3294 r = REGSP 3295 } 3296 i := p.From.Index 3297 if v >= 0 && v < DISP12 { 3298 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3299 } else if v >= -DISP20/2 && v < DISP20/2 { 3300 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3301 } else { 3302 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3303 zRX(op_LA, uint32(p.To.Reg), uint32(r), regtmp(p), uint32(i), asm) 3304 } 3305 3306 case 31: // dword 3307 wd := uint64(c.vregoff(&p.From)) 3308 *asm = append(*asm, 3309 uint8(wd>>56), 3310 uint8(wd>>48), 3311 uint8(wd>>40), 3312 uint8(wd>>32), 3313 uint8(wd>>24), 3314 uint8(wd>>16), 3315 uint8(wd>>8), 3316 uint8(wd)) 3317 3318 case 32: // float op freg freg 3319 var opcode uint32 3320 switch p.As { 3321 default: 3322 c.ctxt.Diag("invalid opcode") 3323 case AFADD: 3324 opcode = op_ADBR 3325 case AFADDS: 3326 opcode = op_AEBR 3327 case AFDIV: 3328 opcode = op_DDBR 3329 case AFDIVS: 3330 opcode = op_DEBR 3331 case AFMUL: 3332 opcode = op_MDBR 3333 case AFMULS: 3334 opcode = op_MEEBR 3335 case AFSUB: 3336 opcode = op_SDBR 3337 case AFSUBS: 3338 opcode = op_SEBR 3339 } 3340 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3341 3342 case 33: // float op [freg] freg 3343 r := p.From.Reg 3344 if oclass(&p.From) == C_NONE { 3345 r = p.To.Reg 3346 } 3347 var opcode uint32 3348 switch p.As { 3349 default: 3350 case AFABS: 3351 opcode = op_LPDBR 3352 case AFNABS: 3353 opcode = op_LNDBR 3354 case ALPDFR: 3355 opcode = op_LPDFR 3356 case ALNDFR: 3357 opcode = op_LNDFR 3358 case AFNEG: 3359 opcode = op_LCDFR 3360 case AFNEGS: 3361 opcode = op_LCEBR 3362 case ALEDBR: 3363 opcode = op_LEDBR 3364 case ALDEBR: 3365 opcode = op_LDEBR 3366 case AFSQRT: 3367 opcode = op_SQDBR 3368 case AFSQRTS: 3369 opcode = op_SQEBR 3370 } 3371 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3372 3373 case 34: // float multiply-add freg freg freg 3374 var opcode uint32 3375 switch p.As { 3376 default: 3377 c.ctxt.Diag("invalid opcode") 3378 case AFMADD: 3379 opcode = op_MADBR 3380 case AFMADDS: 3381 opcode = op_MAEBR 3382 case AFMSUB: 3383 opcode = op_MSDBR 3384 case AFMSUBS: 3385 opcode = op_MSEBR 3386 } 3387 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 3388 3389 case 35: // mov reg mem (no relocation) 3390 d2 := c.regoff(&p.To) 3391 b2 := p.To.Reg 3392 if b2 == 0 { 3393 b2 = REGSP 3394 } 3395 x2 := p.To.Index 3396 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3397 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm) 3398 if x2 != 0 { 3399 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm) 3400 } 3401 x2 = int16(regtmp(p)) 3402 d2 = 0 3403 } 3404 // Emits an RX instruction if an appropriate one exists and the displacement fits in 12 bits. Otherwise use an RXY instruction. 3405 if op, ok := c.zopstore12(p.As); ok && isU12(d2) { 3406 zRX(op, uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3407 } else { 3408 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3409 } 3410 3411 case 36: // mov mem reg (no relocation) 3412 d2 := c.regoff(&p.From) 3413 b2 := p.From.Reg 3414 if b2 == 0 { 3415 b2 = REGSP 3416 } 3417 x2 := p.From.Index 3418 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3419 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm) 3420 if x2 != 0 { 3421 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm) 3422 } 3423 x2 = int16(regtmp(p)) 3424 d2 = 0 3425 } 3426 // Emits an RX instruction if an appropriate one exists and the displacement fits in 12 bits. Otherwise use an RXY instruction. 3427 if op, ok := c.zopload12(p.As); ok && isU12(d2) { 3428 zRX(op, uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3429 } else { 3430 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3431 } 3432 3433 case 40: // word/byte 3434 wd := uint32(c.regoff(&p.From)) 3435 if p.As == AWORD { //WORD 3436 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3437 } else { //BYTE 3438 *asm = append(*asm, uint8(wd)) 3439 } 3440 3441 case 41: // branch on count 3442 r1 := p.From.Reg 3443 ri2 := (p.To.Target().Pc - p.Pc) >> 1 3444 if int64(int16(ri2)) != ri2 { 3445 c.ctxt.Diag("branch target too far away") 3446 } 3447 var opcode uint32 3448 switch p.As { 3449 case ABRCT: 3450 opcode = op_BRCT 3451 case ABRCTG: 3452 opcode = op_BRCTG 3453 } 3454 zRI(opcode, uint32(r1), uint32(ri2), asm) 3455 3456 case 47: // negate [reg] reg 3457 r := p.From.Reg 3458 if r == 0 { 3459 r = p.To.Reg 3460 } 3461 switch p.As { 3462 case ANEG: 3463 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3464 case ANEGW: 3465 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) 3466 } 3467 3468 case 48: // floating-point round to integer 3469 m3 := c.vregoff(&p.From) 3470 if 0 > m3 || m3 > 7 { 3471 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3472 } 3473 var opcode uint32 3474 switch p.As { 3475 case AFIEBR: 3476 opcode = op_FIEBR 3477 case AFIDBR: 3478 opcode = op_FIDBR 3479 } 3480 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3481 3482 case 49: // copysign 3483 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3484 3485 case 50: // load and test 3486 var opcode uint32 3487 switch p.As { 3488 case ALTEBR: 3489 opcode = op_LTEBR 3490 case ALTDBR: 3491 opcode = op_LTDBR 3492 } 3493 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3494 3495 case 51: // test data class (immediate only) 3496 var opcode uint32 3497 switch p.As { 3498 case ATCEB: 3499 opcode = op_TCEB 3500 case ATCDB: 3501 opcode = op_TCDB 3502 } 3503 d2 := c.regoff(&p.To) 3504 zRXE(opcode, uint32(p.From.Reg), 0, 0, uint32(d2), 0, asm) 3505 3506 case 62: // equivalent of Mul64 in math/bits 3507 zRRE(op_MLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3508 3509 case 66: 3510 zRR(op_BCR, uint32(Never), 0, asm) 3511 3512 case 67: // fmov $0 freg 3513 var opcode uint32 3514 switch p.As { 3515 case AFMOVS: 3516 opcode = op_LZER 3517 case AFMOVD: 3518 opcode = op_LZDR 3519 } 3520 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3521 3522 case 68: // movw areg reg 3523 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3524 3525 case 69: // movw reg areg 3526 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3527 3528 case 70: // cmp reg reg 3529 if p.As == ACMPW || p.As == ACMPWU { 3530 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3531 } else { 3532 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3533 } 3534 3535 case 71: // cmp reg $constant 3536 v := c.vregoff(&p.To) 3537 switch p.As { 3538 case ACMP, ACMPW: 3539 if int64(int32(v)) != v { 3540 c.ctxt.Diag("%v overflows an int32", v) 3541 } 3542 case ACMPU, ACMPWU: 3543 if int64(uint32(v)) != v { 3544 c.ctxt.Diag("%v overflows a uint32", v) 3545 } 3546 } 3547 if p.As == ACMP && int64(int16(v)) == v { 3548 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm) 3549 } else if p.As == ACMPW && int64(int16(v)) == v { 3550 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm) 3551 } else { 3552 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm) 3553 } 3554 3555 case 72: // mov $constant mem 3556 v := c.regoff(&p.From) 3557 d := c.regoff(&p.To) 3558 r := p.To.Reg 3559 if p.To.Index != 0 { 3560 c.ctxt.Diag("cannot use index register") 3561 } 3562 if r == 0 { 3563 r = REGSP 3564 } 3565 var opcode uint32 3566 switch p.As { 3567 case AMOVD: 3568 opcode = op_MVGHI 3569 case AMOVW, AMOVWZ: 3570 opcode = op_MVHI 3571 case AMOVH, AMOVHZ: 3572 opcode = op_MVHHI 3573 case AMOVB, AMOVBZ: 3574 opcode = op_MVI 3575 } 3576 if d < 0 || d >= DISP12 { 3577 if r == int16(regtmp(p)) { 3578 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r) 3579 } 3580 if d >= -DISP20/2 && d < DISP20/2 { 3581 if opcode == op_MVI { 3582 opcode = op_MVIY 3583 } else { 3584 zRXY(op_LAY, uint32(regtmp(p)), 0, uint32(r), uint32(d), asm) 3585 r = int16(regtmp(p)) 3586 d = 0 3587 } 3588 } else { 3589 zRIL(_a, op_LGFI, regtmp(p), uint32(d), asm) 3590 zRX(op_LA, regtmp(p), regtmp(p), uint32(r), 0, asm) 3591 r = int16(regtmp(p)) 3592 d = 0 3593 } 3594 } 3595 switch opcode { 3596 case op_MVI: 3597 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3598 case op_MVIY: 3599 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm) 3600 default: 3601 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3602 } 3603 3604 case 74: // mov reg addr (including relocation) 3605 i2 := c.regoff(&p.To) 3606 switch p.As { 3607 case AMOVD: 3608 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3609 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3610 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3611 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3612 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3613 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3614 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3615 adj := uint32(0) // adjustment needed for odd addresses 3616 if i2&1 != 0 { 3617 i2 -= 1 3618 adj = 1 3619 } 3620 zRX(op_STC, uint32(p.From.Reg), 0, regtmp(p), adj, asm) 3621 case AFMOVD: 3622 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3623 zRX(op_STD, uint32(p.From.Reg), 0, regtmp(p), 0, asm) 3624 case AFMOVS: 3625 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3626 zRX(op_STE, uint32(p.From.Reg), 0, regtmp(p), 0, asm) 3627 } 3628 c.addrilreloc(p.To.Sym, int64(i2)) 3629 3630 case 75: // mov addr reg (including relocation) 3631 i2 := c.regoff(&p.From) 3632 switch p.As { 3633 case AMOVD: 3634 if i2&1 != 0 { 3635 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3636 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 1, asm) 3637 i2 -= 1 3638 } else { 3639 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3640 } 3641 case AMOVW: 3642 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3643 case AMOVWZ: 3644 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3645 case AMOVH: 3646 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3647 case AMOVHZ: 3648 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3649 case AMOVB, AMOVBZ: 3650 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3651 adj := uint32(0) // adjustment needed for odd addresses 3652 if i2&1 != 0 { 3653 i2 -= 1 3654 adj = 1 3655 } 3656 switch p.As { 3657 case AMOVB: 3658 zRXY(op_LGB, uint32(p.To.Reg), 0, regtmp(p), adj, asm) 3659 case AMOVBZ: 3660 zRXY(op_LLGC, uint32(p.To.Reg), 0, regtmp(p), adj, asm) 3661 } 3662 case AFMOVD: 3663 zRIL(_a, op_LARL, regtmp(p), 0, asm) 3664 zRX(op_LD, uint32(p.To.Reg), 0, regtmp(p), 0, asm) 3665 case AFMOVS: 3666 zRIL(_a, op_LARL, regtmp(p), 0, asm) 3667 zRX(op_LE, uint32(p.To.Reg), 0, regtmp(p), 0, asm) 3668 } 3669 c.addrilreloc(p.From.Sym, int64(i2)) 3670 3671 case 76: // set program mask 3672 zRR(op_SPM, uint32(p.From.Reg), 0, asm) 3673 3674 case 77: // syscall $constant 3675 if p.From.Offset > 255 || p.From.Offset < 1 { 3676 c.ctxt.Diag("illegal system call; system call number out of range: %v", p) 3677 zE(op_TRAP2, asm) // trap always 3678 } else { 3679 zI(op_SVC, uint32(p.From.Offset), asm) 3680 } 3681 3682 case 78: // undef 3683 // "An instruction consisting entirely of binary 0s is guaranteed 3684 // always to be an illegal instruction." 3685 *asm = append(*asm, 0, 0, 0, 0) 3686 3687 case 79: // compare and swap reg reg reg 3688 v := c.regoff(&p.To) 3689 if v < 0 { 3690 v = 0 3691 } 3692 if p.As == ACS { 3693 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3694 } else if p.As == ACSG { 3695 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3696 } 3697 3698 case 80: // sync 3699 zRR(op_BCR, uint32(NotEqual), 0, asm) 3700 3701 case 81: // float to fixed and fixed to float moves (no conversion) 3702 switch p.As { 3703 case ALDGR: 3704 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3705 case ALGDR: 3706 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3707 } 3708 3709 case 82: // fixed to float conversion 3710 var opcode uint32 3711 switch p.As { 3712 default: 3713 log.Fatalf("unexpected opcode %v", p.As) 3714 case ACEFBRA: 3715 opcode = op_CEFBRA 3716 case ACDFBRA: 3717 opcode = op_CDFBRA 3718 case ACEGBRA: 3719 opcode = op_CEGBRA 3720 case ACDGBRA: 3721 opcode = op_CDGBRA 3722 case ACELFBR: 3723 opcode = op_CELFBR 3724 case ACDLFBR: 3725 opcode = op_CDLFBR 3726 case ACELGBR: 3727 opcode = op_CELGBR 3728 case ACDLGBR: 3729 opcode = op_CDLGBR 3730 } 3731 // set immediate operand M3 to 0 to use the default BFP rounding mode 3732 // (usually round to nearest, ties to even) 3733 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3734 // M4 is reserved and must be 0 3735 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3736 3737 case 83: // float to fixed conversion 3738 var opcode uint32 3739 switch p.As { 3740 default: 3741 log.Fatalf("unexpected opcode %v", p.As) 3742 case ACFEBRA: 3743 opcode = op_CFEBRA 3744 case ACFDBRA: 3745 opcode = op_CFDBRA 3746 case ACGEBRA: 3747 opcode = op_CGEBRA 3748 case ACGDBRA: 3749 opcode = op_CGDBRA 3750 case ACLFEBR: 3751 opcode = op_CLFEBR 3752 case ACLFDBR: 3753 opcode = op_CLFDBR 3754 case ACLGEBR: 3755 opcode = op_CLGEBR 3756 case ACLGDBR: 3757 opcode = op_CLGDBR 3758 } 3759 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3760 // M4 is reserved and must be 0 3761 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3762 3763 case 84: // storage-and-storage operations $length mem mem 3764 l := c.regoff(&p.From) 3765 if l < 1 || l > 256 { 3766 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3767 } 3768 if p.GetFrom3().Index != 0 || p.To.Index != 0 { 3769 c.ctxt.Diag("cannot use index reg") 3770 } 3771 b1 := p.To.Reg 3772 b2 := p.GetFrom3().Reg 3773 if b1 == 0 { 3774 b1 = REGSP 3775 } 3776 if b2 == 0 { 3777 b2 = REGSP 3778 } 3779 d1 := c.regoff(&p.To) 3780 d2 := c.regoff(p.GetFrom3()) 3781 if d1 < 0 || d1 >= DISP12 { 3782 if b2 == int16(regtmp(p)) { 3783 c.ctxt.Diag("regtmp(p) conflict") 3784 } 3785 if b1 != int16(regtmp(p)) { 3786 zRRE(op_LGR, regtmp(p), uint32(b1), asm) 3787 } 3788 zRIL(_a, op_AGFI, regtmp(p), uint32(d1), asm) 3789 if d1 == d2 && b1 == b2 { 3790 d2 = 0 3791 b2 = int16(regtmp(p)) 3792 } 3793 d1 = 0 3794 b1 = int16(regtmp(p)) 3795 } 3796 if d2 < 0 || d2 >= DISP12 { 3797 if b1 == REGTMP2 { 3798 c.ctxt.Diag("REGTMP2 conflict") 3799 } 3800 if b2 != REGTMP2 { 3801 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3802 } 3803 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3804 d2 = 0 3805 b2 = REGTMP2 3806 } 3807 var opcode uint32 3808 switch p.As { 3809 default: 3810 c.ctxt.Diag("unexpected opcode %v", p.As) 3811 case AMVC: 3812 opcode = op_MVC 3813 case AMVCIN: 3814 opcode = op_MVCIN 3815 case ACLC: 3816 opcode = op_CLC 3817 // swap operand order for CLC so that it matches CMP 3818 b1, b2 = b2, b1 3819 d1, d2 = d2, d1 3820 case AXC: 3821 opcode = op_XC 3822 case AOC: 3823 opcode = op_OC 3824 case ANC: 3825 opcode = op_NC 3826 } 3827 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3828 3829 case 85: // load address relative long 3830 v := c.regoff(&p.From) 3831 if p.From.Sym == nil { 3832 if (v & 1) != 0 { 3833 c.ctxt.Diag("cannot use LARL with odd offset: %v", v) 3834 } 3835 } else { 3836 c.addrilreloc(p.From.Sym, int64(v)) 3837 v = 0 3838 } 3839 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3840 3841 case 86: // load address 3842 d := c.vregoff(&p.From) 3843 x := p.From.Index 3844 b := p.From.Reg 3845 if b == 0 { 3846 b = REGSP 3847 } 3848 switch p.As { 3849 case ALA: 3850 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3851 case ALAY: 3852 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3853 } 3854 3855 case 87: // execute relative long 3856 v := c.vregoff(&p.From) 3857 if p.From.Sym == nil { 3858 if v&1 != 0 { 3859 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3860 } 3861 } else { 3862 c.addrilreloc(p.From.Sym, v) 3863 v = 0 3864 } 3865 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3866 3867 case 88: // store clock 3868 var opcode uint32 3869 switch p.As { 3870 case ASTCK: 3871 opcode = op_STCK 3872 case ASTCKC: 3873 opcode = op_STCKC 3874 case ASTCKE: 3875 opcode = op_STCKE 3876 case ASTCKF: 3877 opcode = op_STCKF 3878 } 3879 v := c.vregoff(&p.To) 3880 r := p.To.Reg 3881 if r == 0 { 3882 r = REGSP 3883 } 3884 zS(opcode, uint32(r), uint32(v), asm) 3885 3886 case 89: // compare and branch reg reg 3887 var v int32 3888 if p.To.Target() != nil { 3889 v = int32((p.To.Target().Pc - p.Pc) >> 1) 3890 } 3891 3892 // Some instructions take a mask as the first argument. 3893 r1, r2 := p.From.Reg, p.Reg 3894 if p.From.Type == obj.TYPE_CONST { 3895 r1, r2 = p.Reg, p.RestArgs[0].Reg 3896 } 3897 m3 := uint32(c.branchMask(p)) 3898 3899 var opcode uint32 3900 switch p.As { 3901 case ACRJ: 3902 // COMPARE AND BRANCH RELATIVE (32) 3903 opcode = op_CRJ 3904 case ACGRJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3905 // COMPARE AND BRANCH RELATIVE (64) 3906 opcode = op_CGRJ 3907 case ACLRJ: 3908 // COMPARE LOGICAL AND BRANCH RELATIVE (32) 3909 opcode = op_CLRJ 3910 case ACLGRJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3911 // COMPARE LOGICAL AND BRANCH RELATIVE (64) 3912 opcode = op_CLGRJ 3913 } 3914 3915 if int32(int16(v)) != v { 3916 // The branch is too far for one instruction so crack 3917 // `CMPBEQ x, y, target` into: 3918 // 3919 // CMPBNE x, y, 2(PC) 3920 // BR target 3921 // 3922 // Note that the instruction sequence MUST NOT clobber 3923 // the condition code. 3924 m3 ^= 0xe // invert 3-bit mask 3925 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(sizeRIE+sizeRIL)/2, 0, 0, m3, 0, asm) 3926 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm) 3927 } else { 3928 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(v), 0, 0, m3, 0, asm) 3929 } 3930 3931 case 90: // compare and branch reg $constant 3932 var v int32 3933 if p.To.Target() != nil { 3934 v = int32((p.To.Target().Pc - p.Pc) >> 1) 3935 } 3936 3937 // Some instructions take a mask as the first argument. 3938 r1, i2 := p.From.Reg, p.RestArgs[0].Offset 3939 if p.From.Type == obj.TYPE_CONST { 3940 r1 = p.Reg 3941 } 3942 m3 := uint32(c.branchMask(p)) 3943 3944 var opcode uint32 3945 switch p.As { 3946 case ACIJ: 3947 opcode = op_CIJ 3948 case ACGIJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3949 opcode = op_CGIJ 3950 case ACLIJ: 3951 opcode = op_CLIJ 3952 case ACLGIJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3953 opcode = op_CLGIJ 3954 } 3955 if int32(int16(v)) != v { 3956 // The branch is too far for one instruction so crack 3957 // `CMPBEQ x, $0, target` into: 3958 // 3959 // CMPBNE x, $0, 2(PC) 3960 // BR target 3961 // 3962 // Note that the instruction sequence MUST NOT clobber 3963 // the condition code. 3964 m3 ^= 0xe // invert 3-bit mask 3965 zRIE(_c, opcode, uint32(r1), m3, uint32(sizeRIE+sizeRIL)/2, 0, 0, 0, uint32(i2), asm) 3966 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm) 3967 } else { 3968 zRIE(_c, opcode, uint32(r1), m3, uint32(v), 0, 0, 0, uint32(i2), asm) 3969 } 3970 3971 case 91: // test under mask (immediate) 3972 var opcode uint32 3973 switch p.As { 3974 case ATMHH: 3975 opcode = op_TMHH 3976 case ATMHL: 3977 opcode = op_TMHL 3978 case ATMLH: 3979 opcode = op_TMLH 3980 case ATMLL: 3981 opcode = op_TMLL 3982 } 3983 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm) 3984 3985 case 92: // insert program mask 3986 zRRE(op_IPM, uint32(p.From.Reg), 0, asm) 3987 3988 case 93: // GOT lookup 3989 v := c.vregoff(&p.To) 3990 if v != 0 { 3991 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3992 } 3993 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3994 rel := obj.Addrel(c.cursym) 3995 rel.Off = int32(c.pc + 2) 3996 rel.Siz = 4 3997 rel.Sym = p.From.Sym 3998 rel.Type = objabi.R_GOTPCREL 3999 rel.Add = 2 + int64(rel.Siz) 4000 4001 case 94: // TLS local exec model 4002 zRIL(_b, op_LARL, regtmp(p), (sizeRIL+sizeRXY+sizeRI)>>1, asm) 4003 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 0, asm) 4004 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 4005 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 4006 rel := obj.Addrel(c.cursym) 4007 rel.Off = int32(c.pc + sizeRIL + sizeRXY + sizeRI) 4008 rel.Siz = 8 4009 rel.Sym = p.From.Sym 4010 rel.Type = objabi.R_TLS_LE 4011 rel.Add = 0 4012 4013 case 95: // TLS initial exec model 4014 // Assembly | Relocation symbol | Done Here? 4015 // -------------------------------------------------------------- 4016 // ear %r11, %a0 | | 4017 // sllg %r11, %r11, 32 | | 4018 // ear %r11, %a1 | | 4019 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 4020 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 4021 // la %r10, 0(%r10, %r11) | | 4022 // -------------------------------------------------------------- 4023 4024 // R_390_TLS_IEENT 4025 zRIL(_b, op_LARL, regtmp(p), 0, asm) 4026 ieent := obj.Addrel(c.cursym) 4027 ieent.Off = int32(c.pc + 2) 4028 ieent.Siz = 4 4029 ieent.Sym = p.From.Sym 4030 ieent.Type = objabi.R_TLS_IE 4031 ieent.Add = 2 + int64(ieent.Siz) 4032 4033 // R_390_TLS_LOAD 4034 zRXY(op_LGF, uint32(p.To.Reg), regtmp(p), 0, 0, asm) 4035 // TODO(mundaym): add R_390_TLS_LOAD relocation here 4036 // not strictly required but might allow the linker to optimize 4037 4038 case 96: // clear macro 4039 length := c.vregoff(&p.From) 4040 offset := c.vregoff(&p.To) 4041 reg := p.To.Reg 4042 if reg == 0 { 4043 reg = REGSP 4044 } 4045 if length <= 0 { 4046 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 4047 } 4048 for length > 0 { 4049 if offset < 0 || offset >= DISP12 { 4050 if offset >= -DISP20/2 && offset < DISP20/2 { 4051 zRXY(op_LAY, regtmp(p), uint32(reg), 0, uint32(offset), asm) 4052 } else { 4053 if reg != int16(regtmp(p)) { 4054 zRRE(op_LGR, regtmp(p), uint32(reg), asm) 4055 } 4056 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm) 4057 } 4058 reg = int16(regtmp(p)) 4059 offset = 0 4060 } 4061 size := length 4062 if size > 256 { 4063 size = 256 4064 } 4065 4066 switch size { 4067 case 1: 4068 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 4069 case 2: 4070 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 4071 case 4: 4072 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 4073 case 8: 4074 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 4075 default: 4076 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 4077 } 4078 4079 length -= size 4080 offset += size 4081 } 4082 4083 case 97: // store multiple 4084 rstart := p.From.Reg 4085 rend := p.Reg 4086 offset := c.regoff(&p.To) 4087 reg := p.To.Reg 4088 if reg == 0 { 4089 reg = REGSP 4090 } 4091 if offset < -DISP20/2 || offset >= DISP20/2 { 4092 if reg != int16(regtmp(p)) { 4093 zRRE(op_LGR, regtmp(p), uint32(reg), asm) 4094 } 4095 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm) 4096 reg = int16(regtmp(p)) 4097 offset = 0 4098 } 4099 switch p.As { 4100 case ASTMY: 4101 if offset >= 0 && offset < DISP12 { 4102 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4103 } else { 4104 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4105 } 4106 case ASTMG: 4107 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4108 } 4109 4110 case 98: // load multiple 4111 rstart := p.Reg 4112 rend := p.To.Reg 4113 offset := c.regoff(&p.From) 4114 reg := p.From.Reg 4115 if reg == 0 { 4116 reg = REGSP 4117 } 4118 if offset < -DISP20/2 || offset >= DISP20/2 { 4119 if reg != int16(regtmp(p)) { 4120 zRRE(op_LGR, regtmp(p), uint32(reg), asm) 4121 } 4122 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm) 4123 reg = int16(regtmp(p)) 4124 offset = 0 4125 } 4126 switch p.As { 4127 case ALMY: 4128 if offset >= 0 && offset < DISP12 { 4129 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4130 } else { 4131 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4132 } 4133 case ALMG: 4134 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4135 } 4136 4137 case 99: // interlocked load and op 4138 if p.To.Index != 0 { 4139 c.ctxt.Diag("cannot use indexed address") 4140 } 4141 offset := c.regoff(&p.To) 4142 if offset < -DISP20/2 || offset >= DISP20/2 { 4143 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 4144 } 4145 var opcode uint32 4146 switch p.As { 4147 case ALAA: 4148 opcode = op_LAA 4149 case ALAAG: 4150 opcode = op_LAAG 4151 case ALAAL: 4152 opcode = op_LAAL 4153 case ALAALG: 4154 opcode = op_LAALG 4155 case ALAN: 4156 opcode = op_LAN 4157 case ALANG: 4158 opcode = op_LANG 4159 case ALAX: 4160 opcode = op_LAX 4161 case ALAXG: 4162 opcode = op_LAXG 4163 case ALAO: 4164 opcode = op_LAO 4165 case ALAOG: 4166 opcode = op_LAOG 4167 } 4168 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 4169 4170 case 100: // VRX STORE 4171 op, m3, _ := vop(p.As) 4172 v1 := p.From.Reg 4173 if p.Reg != 0 { 4174 m3 = uint32(c.vregoff(&p.From)) 4175 v1 = p.Reg 4176 } 4177 b2 := p.To.Reg 4178 if b2 == 0 { 4179 b2 = REGSP 4180 } 4181 d2 := uint32(c.vregoff(&p.To)) 4182 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm) 4183 4184 case 101: // VRX LOAD 4185 op, m3, _ := vop(p.As) 4186 src := &p.From 4187 if p.GetFrom3() != nil { 4188 m3 = uint32(c.vregoff(&p.From)) 4189 src = p.GetFrom3() 4190 } 4191 b2 := src.Reg 4192 if b2 == 0 { 4193 b2 = REGSP 4194 } 4195 d2 := uint32(c.vregoff(src)) 4196 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm) 4197 4198 case 102: // VRV SCATTER 4199 op, _, _ := vop(p.As) 4200 m3 := uint32(c.vregoff(&p.From)) 4201 b2 := p.To.Reg 4202 if b2 == 0 { 4203 b2 = REGSP 4204 } 4205 d2 := uint32(c.vregoff(&p.To)) 4206 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 4207 4208 case 103: // VRV GATHER 4209 op, _, _ := vop(p.As) 4210 m3 := uint32(c.vregoff(&p.From)) 4211 b2 := p.GetFrom3().Reg 4212 if b2 == 0 { 4213 b2 = REGSP 4214 } 4215 d2 := uint32(c.vregoff(p.GetFrom3())) 4216 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm) 4217 4218 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 4219 op, m4, _ := vop(p.As) 4220 fr := p.Reg 4221 if fr == 0 { 4222 fr = p.To.Reg 4223 } 4224 bits := uint32(c.vregoff(&p.From)) 4225 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 4226 4227 case 105: // VRS STORE MULTIPLE 4228 op, _, _ := vop(p.As) 4229 offset := uint32(c.vregoff(&p.To)) 4230 reg := p.To.Reg 4231 if reg == 0 { 4232 reg = REGSP 4233 } 4234 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 4235 4236 case 106: // VRS LOAD MULTIPLE 4237 op, _, _ := vop(p.As) 4238 offset := uint32(c.vregoff(&p.From)) 4239 reg := p.From.Reg 4240 if reg == 0 { 4241 reg = REGSP 4242 } 4243 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 4244 4245 case 107: // VRS STORE WITH LENGTH 4246 op, _, _ := vop(p.As) 4247 offset := uint32(c.vregoff(&p.To)) 4248 reg := p.To.Reg 4249 if reg == 0 { 4250 reg = REGSP 4251 } 4252 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 4253 4254 case 108: // VRS LOAD WITH LENGTH 4255 op, _, _ := vop(p.As) 4256 offset := uint32(c.vregoff(p.GetFrom3())) 4257 reg := p.GetFrom3().Reg 4258 if reg == 0 { 4259 reg = REGSP 4260 } 4261 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 4262 4263 case 109: // VRI-a 4264 op, m3, _ := vop(p.As) 4265 i2 := uint32(c.vregoff(&p.From)) 4266 if p.GetFrom3() != nil { 4267 m3 = uint32(c.vregoff(&p.From)) 4268 i2 = uint32(c.vregoff(p.GetFrom3())) 4269 } 4270 switch p.As { 4271 case AVZERO: 4272 i2 = 0 4273 case AVONE: 4274 i2 = 0xffff 4275 } 4276 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 4277 4278 case 110: 4279 op, m4, _ := vop(p.As) 4280 i2 := uint32(c.vregoff(&p.From)) 4281 i3 := uint32(c.vregoff(p.GetFrom3())) 4282 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 4283 4284 case 111: 4285 op, m4, _ := vop(p.As) 4286 i2 := uint32(c.vregoff(&p.From)) 4287 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 4288 4289 case 112: 4290 op, m5, _ := vop(p.As) 4291 i4 := uint32(c.vregoff(&p.From)) 4292 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm) 4293 4294 case 113: 4295 op, m4, _ := vop(p.As) 4296 m5 := singleElementMask(p.As) 4297 i3 := uint32(c.vregoff(&p.From)) 4298 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 4299 4300 case 114: // VRR-a 4301 op, m3, m5 := vop(p.As) 4302 m4 := singleElementMask(p.As) 4303 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 4304 4305 case 115: // VRR-a COMPARE 4306 op, m3, m5 := vop(p.As) 4307 m4 := singleElementMask(p.As) 4308 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 4309 4310 case 117: // VRR-b 4311 op, m4, m5 := vop(p.As) 4312 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4313 4314 case 118: // VRR-c 4315 op, m4, m6 := vop(p.As) 4316 m5 := singleElementMask(p.As) 4317 v3 := p.Reg 4318 if v3 == 0 { 4319 v3 = p.To.Reg 4320 } 4321 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4322 4323 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4324 op, m4, m6 := vop(p.As) 4325 m5 := singleElementMask(p.As) 4326 v2 := p.Reg 4327 if v2 == 0 { 4328 v2 = p.To.Reg 4329 } 4330 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4331 4332 case 120: // VRR-d 4333 op, m6, _ := vop(p.As) 4334 m5 := singleElementMask(p.As) 4335 v1 := uint32(p.To.Reg) 4336 v2 := uint32(p.From.Reg) 4337 v3 := uint32(p.Reg) 4338 v4 := uint32(p.GetFrom3().Reg) 4339 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4340 4341 case 121: // VRR-e 4342 op, m6, _ := vop(p.As) 4343 m5 := singleElementMask(p.As) 4344 v1 := uint32(p.To.Reg) 4345 v2 := uint32(p.From.Reg) 4346 v3 := uint32(p.Reg) 4347 v4 := uint32(p.GetFrom3().Reg) 4348 zVRRe(op, v1, v2, v3, m6, m5, v4, asm) 4349 4350 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4351 op, _, _ := vop(p.As) 4352 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4353 4354 case 123: // VPDI $m4, V2, V3, V1 4355 op, _, _ := vop(p.As) 4356 m4 := c.regoff(&p.From) 4357 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm) 4358 } 4359 } 4360 4361 func (c *ctxtz) vregoff(a *obj.Addr) int64 { 4362 c.instoffset = 0 4363 if a != nil { 4364 c.aclass(a) 4365 } 4366 return c.instoffset 4367 } 4368 4369 func (c *ctxtz) regoff(a *obj.Addr) int32 { 4370 return int32(c.vregoff(a)) 4371 } 4372 4373 // find if the displacement is within 12 bit 4374 func isU12(displacement int32) bool { 4375 return displacement >= 0 && displacement < DISP12 4376 } 4377 4378 // zopload12 returns the RX op with 12 bit displacement for the given load 4379 func (c *ctxtz) zopload12(a obj.As) (uint32, bool) { 4380 switch a { 4381 case AFMOVD: 4382 return op_LD, true 4383 case AFMOVS: 4384 return op_LE, true 4385 } 4386 return 0, false 4387 } 4388 4389 // zopload returns the RXY op for the given load 4390 func (c *ctxtz) zopload(a obj.As) uint32 { 4391 switch a { 4392 // fixed point load 4393 case AMOVD: 4394 return op_LG 4395 case AMOVW: 4396 return op_LGF 4397 case AMOVWZ: 4398 return op_LLGF 4399 case AMOVH: 4400 return op_LGH 4401 case AMOVHZ: 4402 return op_LLGH 4403 case AMOVB: 4404 return op_LGB 4405 case AMOVBZ: 4406 return op_LLGC 4407 4408 // floating point load 4409 case AFMOVD: 4410 return op_LDY 4411 case AFMOVS: 4412 return op_LEY 4413 4414 // byte reversed load 4415 case AMOVDBR: 4416 return op_LRVG 4417 case AMOVWBR: 4418 return op_LRV 4419 case AMOVHBR: 4420 return op_LRVH 4421 } 4422 4423 c.ctxt.Diag("unknown store opcode %v", a) 4424 return 0 4425 } 4426 4427 // zopstore12 returns the RX op with 12 bit displacement for the given store 4428 func (c *ctxtz) zopstore12(a obj.As) (uint32, bool) { 4429 switch a { 4430 case AFMOVD: 4431 return op_STD, true 4432 case AFMOVS: 4433 return op_STE, true 4434 case AMOVW, AMOVWZ: 4435 return op_ST, true 4436 case AMOVH, AMOVHZ: 4437 return op_STH, true 4438 case AMOVB, AMOVBZ: 4439 return op_STC, true 4440 } 4441 return 0, false 4442 } 4443 4444 // zopstore returns the RXY op for the given store 4445 func (c *ctxtz) zopstore(a obj.As) uint32 { 4446 switch a { 4447 // fixed point store 4448 case AMOVD: 4449 return op_STG 4450 case AMOVW, AMOVWZ: 4451 return op_STY 4452 case AMOVH, AMOVHZ: 4453 return op_STHY 4454 case AMOVB, AMOVBZ: 4455 return op_STCY 4456 4457 // floating point store 4458 case AFMOVD: 4459 return op_STDY 4460 case AFMOVS: 4461 return op_STEY 4462 4463 // byte reversed store 4464 case AMOVDBR: 4465 return op_STRVG 4466 case AMOVWBR: 4467 return op_STRV 4468 case AMOVHBR: 4469 return op_STRVH 4470 } 4471 4472 c.ctxt.Diag("unknown store opcode %v", a) 4473 return 0 4474 } 4475 4476 // zoprre returns the RRE op for the given a 4477 func (c *ctxtz) zoprre(a obj.As) uint32 { 4478 switch a { 4479 case ACMP: 4480 return op_CGR 4481 case ACMPU: 4482 return op_CLGR 4483 case AFCMPO: //ordered 4484 return op_KDBR 4485 case AFCMPU: //unordered 4486 return op_CDBR 4487 case ACEBR: 4488 return op_CEBR 4489 } 4490 c.ctxt.Diag("unknown rre opcode %v", a) 4491 return 0 4492 } 4493 4494 // zoprr returns the RR op for the given a 4495 func (c *ctxtz) zoprr(a obj.As) uint32 { 4496 switch a { 4497 case ACMPW: 4498 return op_CR 4499 case ACMPWU: 4500 return op_CLR 4501 } 4502 c.ctxt.Diag("unknown rr opcode %v", a) 4503 return 0 4504 } 4505 4506 // zopril returns the RIL op for the given a 4507 func (c *ctxtz) zopril(a obj.As) uint32 { 4508 switch a { 4509 case ACMP: 4510 return op_CGFI 4511 case ACMPU: 4512 return op_CLGFI 4513 case ACMPW: 4514 return op_CFI 4515 case ACMPWU: 4516 return op_CLFI 4517 } 4518 c.ctxt.Diag("unknown ril opcode %v", a) 4519 return 0 4520 } 4521 4522 // z instructions sizes 4523 const ( 4524 sizeE = 2 4525 sizeI = 2 4526 sizeIE = 4 4527 sizeMII = 6 4528 sizeRI = 4 4529 sizeRI1 = 4 4530 sizeRI2 = 4 4531 sizeRI3 = 4 4532 sizeRIE = 6 4533 sizeRIE1 = 6 4534 sizeRIE2 = 6 4535 sizeRIE3 = 6 4536 sizeRIE4 = 6 4537 sizeRIE5 = 6 4538 sizeRIE6 = 6 4539 sizeRIL = 6 4540 sizeRIL1 = 6 4541 sizeRIL2 = 6 4542 sizeRIL3 = 6 4543 sizeRIS = 6 4544 sizeRR = 2 4545 sizeRRD = 4 4546 sizeRRE = 4 4547 sizeRRF = 4 4548 sizeRRF1 = 4 4549 sizeRRF2 = 4 4550 sizeRRF3 = 4 4551 sizeRRF4 = 4 4552 sizeRRF5 = 4 4553 sizeRRR = 2 4554 sizeRRS = 6 4555 sizeRS = 4 4556 sizeRS1 = 4 4557 sizeRS2 = 4 4558 sizeRSI = 4 4559 sizeRSL = 6 4560 sizeRSY = 6 4561 sizeRSY1 = 6 4562 sizeRSY2 = 6 4563 sizeRX = 4 4564 sizeRX1 = 4 4565 sizeRX2 = 4 4566 sizeRXE = 6 4567 sizeRXF = 6 4568 sizeRXY = 6 4569 sizeRXY1 = 6 4570 sizeRXY2 = 6 4571 sizeS = 4 4572 sizeSI = 4 4573 sizeSIL = 6 4574 sizeSIY = 6 4575 sizeSMI = 6 4576 sizeSS = 6 4577 sizeSS1 = 6 4578 sizeSS2 = 6 4579 sizeSS3 = 6 4580 sizeSS4 = 6 4581 sizeSS5 = 6 4582 sizeSS6 = 6 4583 sizeSSE = 6 4584 sizeSSF = 6 4585 ) 4586 4587 // instruction format variations 4588 type form int 4589 4590 const ( 4591 _a form = iota 4592 _b 4593 _c 4594 _d 4595 _e 4596 _f 4597 ) 4598 4599 func zE(op uint32, asm *[]byte) { 4600 *asm = append(*asm, uint8(op>>8), uint8(op)) 4601 } 4602 4603 func zI(op, i1 uint32, asm *[]byte) { 4604 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4605 } 4606 4607 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4608 *asm = append(*asm, 4609 uint8(op>>8), 4610 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4611 uint8(ri2), 4612 uint8(ri3>>16), 4613 uint8(ri3>>8), 4614 uint8(ri3)) 4615 } 4616 4617 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4618 *asm = append(*asm, 4619 uint8(op>>8), 4620 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4621 uint8(i2_ri2>>8), 4622 uint8(i2_ri2)) 4623 } 4624 4625 // Expected argument values for the instruction formats. 4626 // 4627 // Format a1 a2 a3 a4 a5 a6 a7 4628 // ------------------------------------ 4629 // a r1, 0, i2, 0, 0, m3, 0 4630 // b r1, r2, ri4, 0, 0, m3, 0 4631 // c r1, m3, ri4, 0, 0, 0, i2 4632 // d r1, r3, i2, 0, 0, 0, 0 4633 // e r1, r3, ri2, 0, 0, 0, 0 4634 // f r1, r2, 0, i3, i4, 0, i5 4635 // g r1, m3, i2, 0, 0, 0, 0 4636 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4637 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4638 4639 switch f { 4640 default: 4641 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4642 case _f: 4643 *asm = append(*asm, uint8(i3), uint8(i4)) 4644 } 4645 4646 switch f { 4647 case _a, _b: 4648 *asm = append(*asm, uint8(m3)<<4) 4649 default: 4650 *asm = append(*asm, uint8(i2_i5)) 4651 } 4652 4653 *asm = append(*asm, uint8(op)) 4654 } 4655 4656 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4657 if f == _a || f == _b { 4658 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4659 } 4660 *asm = append(*asm, 4661 uint8(op>>8), 4662 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4663 uint8(i2_ri2>>24), 4664 uint8(i2_ri2>>16), 4665 uint8(i2_ri2>>8), 4666 uint8(i2_ri2)) 4667 } 4668 4669 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4670 *asm = append(*asm, 4671 uint8(op>>8), 4672 (uint8(r1)<<4)|uint8(m3&0x0F), 4673 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4674 uint8(d4), 4675 uint8(i2), 4676 uint8(op)) 4677 } 4678 4679 func zRR(op, r1, r2 uint32, asm *[]byte) { 4680 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4681 } 4682 4683 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4684 *asm = append(*asm, 4685 uint8(op>>8), 4686 uint8(op), 4687 uint8(r1)<<4, 4688 (uint8(r3)<<4)|uint8(r2&0x0F)) 4689 } 4690 4691 func zRRE(op, r1, r2 uint32, asm *[]byte) { 4692 *asm = append(*asm, 4693 uint8(op>>8), 4694 uint8(op), 4695 0, 4696 (uint8(r1)<<4)|uint8(r2&0x0F)) 4697 } 4698 4699 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4700 *asm = append(*asm, 4701 uint8(op>>8), 4702 uint8(op), 4703 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4704 (uint8(r1)<<4)|uint8(r2&0x0F)) 4705 } 4706 4707 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4708 *asm = append(*asm, 4709 uint8(op>>8), 4710 (uint8(r1)<<4)|uint8(r2&0x0F), 4711 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4712 uint8(d4), 4713 uint8(m3)<<4, 4714 uint8(op)) 4715 } 4716 4717 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4718 *asm = append(*asm, 4719 uint8(op>>8), 4720 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4721 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4722 uint8(d2)) 4723 } 4724 4725 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4726 *asm = append(*asm, 4727 uint8(op>>8), 4728 (uint8(r1)<<4)|uint8(r3&0x0F), 4729 uint8(ri2>>8), 4730 uint8(ri2)) 4731 } 4732 4733 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4734 *asm = append(*asm, 4735 uint8(op>>8), 4736 uint8(l1), 4737 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4738 uint8(d2), 4739 uint8(op)) 4740 } 4741 4742 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4743 dl2 := uint16(d2) & 0x0FFF 4744 *asm = append(*asm, 4745 uint8(op>>8), 4746 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4747 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4748 uint8(dl2), 4749 uint8(d2>>12), 4750 uint8(op)) 4751 } 4752 4753 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4754 *asm = append(*asm, 4755 uint8(op>>8), 4756 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4757 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4758 uint8(d2)) 4759 } 4760 4761 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4762 *asm = append(*asm, 4763 uint8(op>>8), 4764 (uint8(r1)<<4)|uint8(x2&0x0F), 4765 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4766 uint8(d2), 4767 uint8(m3)<<4, 4768 uint8(op)) 4769 } 4770 4771 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4772 *asm = append(*asm, 4773 uint8(op>>8), 4774 (uint8(r3)<<4)|uint8(x2&0x0F), 4775 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4776 uint8(d2), 4777 uint8(m1)<<4, 4778 uint8(op)) 4779 } 4780 4781 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4782 dl2 := uint16(d2) & 0x0FFF 4783 *asm = append(*asm, 4784 uint8(op>>8), 4785 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4786 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4787 uint8(dl2), 4788 uint8(d2>>12), 4789 uint8(op)) 4790 } 4791 4792 func zS(op, b2, d2 uint32, asm *[]byte) { 4793 *asm = append(*asm, 4794 uint8(op>>8), 4795 uint8(op), 4796 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4797 uint8(d2)) 4798 } 4799 4800 func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4801 *asm = append(*asm, 4802 uint8(op>>8), 4803 uint8(i2), 4804 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4805 uint8(d1)) 4806 } 4807 4808 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4809 *asm = append(*asm, 4810 uint8(op>>8), 4811 uint8(op), 4812 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4813 uint8(d1), 4814 uint8(i2>>8), 4815 uint8(i2)) 4816 } 4817 4818 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4819 dl1 := uint16(d1) & 0x0FFF 4820 *asm = append(*asm, 4821 uint8(op>>8), 4822 uint8(i2), 4823 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4824 uint8(dl1), 4825 uint8(d1>>12), 4826 uint8(op)) 4827 } 4828 4829 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4830 *asm = append(*asm, 4831 uint8(op>>8), 4832 uint8(m1)<<4, 4833 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4834 uint8(d3), 4835 uint8(ri2>>8), 4836 uint8(ri2)) 4837 } 4838 4839 // Expected argument values for the instruction formats. 4840 // 4841 // Format a1 a2 a3 a4 a5 a6 4842 // ------------------------------- 4843 // a l1, 0, b1, d1, b2, d2 4844 // b l1, l2, b1, d1, b2, d2 4845 // c l1, i3, b1, d1, b2, d2 4846 // d r1, r3, b1, d1, b2, d2 4847 // e r1, r3, b2, d2, b4, d4 4848 // f 0, l2, b1, d1, b2, d2 4849 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4850 *asm = append(*asm, uint8(op>>8)) 4851 4852 switch f { 4853 case _a: 4854 *asm = append(*asm, uint8(l1_r1)) 4855 case _b, _c, _d, _e: 4856 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4857 case _f: 4858 *asm = append(*asm, uint8(l2_i3_r3)) 4859 } 4860 4861 *asm = append(*asm, 4862 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4863 uint8(d1_d2), 4864 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4865 uint8(d2_d4)) 4866 } 4867 4868 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4869 *asm = append(*asm, 4870 uint8(op>>8), 4871 uint8(op), 4872 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4873 uint8(d1), 4874 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4875 uint8(d2)) 4876 } 4877 4878 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4879 *asm = append(*asm, 4880 uint8(op>>8), 4881 (uint8(r3)<<4)|(uint8(op)&0x0F), 4882 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4883 uint8(d1), 4884 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4885 uint8(d2)) 4886 } 4887 4888 func rxb(va, vb, vc, vd uint32) uint8 { 4889 mask := uint8(0) 4890 if va >= REG_V16 && va <= REG_V31 { 4891 mask |= 0x8 4892 } 4893 if vb >= REG_V16 && vb <= REG_V31 { 4894 mask |= 0x4 4895 } 4896 if vc >= REG_V16 && vc <= REG_V31 { 4897 mask |= 0x2 4898 } 4899 if vd >= REG_V16 && vd <= REG_V31 { 4900 mask |= 0x1 4901 } 4902 return mask 4903 } 4904 4905 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 4906 *asm = append(*asm, 4907 uint8(op>>8), 4908 (uint8(v1)<<4)|(uint8(x2)&0xf), 4909 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4910 uint8(d2), 4911 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4912 uint8(op)) 4913 } 4914 4915 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 4916 *asm = append(*asm, 4917 uint8(op>>8), 4918 (uint8(v1)<<4)|(uint8(v2)&0xf), 4919 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4920 uint8(d2), 4921 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4922 uint8(op)) 4923 } 4924 4925 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 4926 *asm = append(*asm, 4927 uint8(op>>8), 4928 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 4929 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4930 uint8(d2), 4931 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 4932 uint8(op)) 4933 } 4934 4935 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 4936 *asm = append(*asm, 4937 uint8(op>>8), 4938 (uint8(v1)<<4)|(uint8(v2)&0xf), 4939 0, 4940 (uint8(m5)<<4)|(uint8(m4)&0xf), 4941 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4942 uint8(op)) 4943 } 4944 4945 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 4946 *asm = append(*asm, 4947 uint8(op>>8), 4948 (uint8(v1)<<4)|(uint8(v2)&0xf), 4949 uint8(v3)<<4, 4950 uint8(m5)<<4, 4951 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4952 uint8(op)) 4953 } 4954 4955 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 4956 *asm = append(*asm, 4957 uint8(op>>8), 4958 (uint8(v1)<<4)|(uint8(v2)&0xf), 4959 uint8(v3)<<4, 4960 (uint8(m6)<<4)|(uint8(m5)&0xf), 4961 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4962 uint8(op)) 4963 } 4964 4965 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 4966 *asm = append(*asm, 4967 uint8(op>>8), 4968 (uint8(v1)<<4)|(uint8(v2)&0xf), 4969 (uint8(v3)<<4)|(uint8(m5)&0xf), 4970 uint8(m6)<<4, 4971 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4972 uint8(op)) 4973 } 4974 4975 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 4976 *asm = append(*asm, 4977 uint8(op>>8), 4978 (uint8(v1)<<4)|(uint8(v2)&0xf), 4979 (uint8(v3)<<4)|(uint8(m6)&0xf), 4980 uint8(m5), 4981 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4982 uint8(op)) 4983 } 4984 4985 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 4986 *asm = append(*asm, 4987 uint8(op>>8), 4988 (uint8(v1)<<4)|(uint8(r2)&0xf), 4989 uint8(r3)<<4, 4990 0, 4991 rxb(v1, 0, 0, 0), 4992 uint8(op)) 4993 } 4994 4995 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 4996 *asm = append(*asm, 4997 uint8(op>>8), 4998 uint8(v1)<<4, 4999 uint8(i2>>8), 5000 uint8(i2), 5001 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 5002 uint8(op)) 5003 } 5004 5005 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 5006 *asm = append(*asm, 5007 uint8(op>>8), 5008 uint8(v1)<<4, 5009 uint8(i2), 5010 uint8(i3), 5011 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 5012 uint8(op)) 5013 } 5014 5015 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 5016 *asm = append(*asm, 5017 uint8(op>>8), 5018 (uint8(v1)<<4)|(uint8(v3)&0xf), 5019 uint8(i2>>8), 5020 uint8(i2), 5021 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 5022 uint8(op)) 5023 } 5024 5025 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 5026 *asm = append(*asm, 5027 uint8(op>>8), 5028 (uint8(v1)<<4)|(uint8(v2)&0xf), 5029 uint8(v3)<<4, 5030 uint8(i4), 5031 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 5032 uint8(op)) 5033 } 5034 5035 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 5036 *asm = append(*asm, 5037 uint8(op>>8), 5038 (uint8(v1)<<4)|(uint8(v2)&0xf), 5039 uint8(i3>>4), 5040 (uint8(i3)<<4)|(uint8(m5)&0xf), 5041 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 5042 uint8(op)) 5043 }