cpu.go (11354B)
1 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 2 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 3 // Portions Copyright © 1997-1999 Vita Nuova Limited 4 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 5 // Portions Copyright © 2004,2006 Bruce Ellis 6 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 7 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 8 // Portions Copyright © 2009 The Go Authors. All rights reserved. 9 // Portions Copyright © 2019 The Go Authors. All rights reserved. 10 // 11 // Permission is hereby granted, free of charge, to any person obtaining a copy 12 // of this software and associated documentation files (the "Software"), to deal 13 // in the Software without restriction, including without limitation the rights 14 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 15 // copies of the Software, and to permit persons to whom the Software is 16 // furnished to do so, subject to the following conditions: 17 // 18 // The above copyright notice and this permission notice shall be included in 19 // all copies or substantial portions of the Software. 20 // 21 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 24 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 26 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 27 // THE SOFTWARE. 28 29 package riscv 30 31 import "github.com/twitchyliquid64/golang-asm/obj" 32 33 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv 34 35 const ( 36 // Base register numberings. 37 REG_X0 = obj.RBaseRISCV + iota 38 REG_X1 39 REG_X2 40 REG_X3 41 REG_X4 42 REG_X5 43 REG_X6 44 REG_X7 45 REG_X8 46 REG_X9 47 REG_X10 48 REG_X11 49 REG_X12 50 REG_X13 51 REG_X14 52 REG_X15 53 REG_X16 54 REG_X17 55 REG_X18 56 REG_X19 57 REG_X20 58 REG_X21 59 REG_X22 60 REG_X23 61 REG_X24 62 REG_X25 63 REG_X26 64 REG_X27 65 REG_X28 66 REG_X29 67 REG_X30 68 REG_X31 69 70 // FP register numberings. 71 REG_F0 72 REG_F1 73 REG_F2 74 REG_F3 75 REG_F4 76 REG_F5 77 REG_F6 78 REG_F7 79 REG_F8 80 REG_F9 81 REG_F10 82 REG_F11 83 REG_F12 84 REG_F13 85 REG_F14 86 REG_F15 87 REG_F16 88 REG_F17 89 REG_F18 90 REG_F19 91 REG_F20 92 REG_F21 93 REG_F22 94 REG_F23 95 REG_F24 96 REG_F25 97 REG_F26 98 REG_F27 99 REG_F28 100 REG_F29 101 REG_F30 102 REG_F31 103 104 // This marks the end of the register numbering. 105 REG_END 106 107 // General registers reassigned to ABI names. 108 REG_ZERO = REG_X0 109 REG_RA = REG_X1 // aka REG_LR 110 REG_SP = REG_X2 111 REG_GP = REG_X3 // aka REG_SB 112 REG_TP = REG_X4 // aka REG_G 113 REG_T0 = REG_X5 114 REG_T1 = REG_X6 115 REG_T2 = REG_X7 116 REG_S0 = REG_X8 117 REG_S1 = REG_X9 118 REG_A0 = REG_X10 119 REG_A1 = REG_X11 120 REG_A2 = REG_X12 121 REG_A3 = REG_X13 122 REG_A4 = REG_X14 123 REG_A5 = REG_X15 124 REG_A6 = REG_X16 125 REG_A7 = REG_X17 126 REG_S2 = REG_X18 127 REG_S3 = REG_X19 128 REG_S4 = REG_X20 // aka REG_CTXT 129 REG_S5 = REG_X21 130 REG_S6 = REG_X22 131 REG_S7 = REG_X23 132 REG_S8 = REG_X24 133 REG_S9 = REG_X25 134 REG_S10 = REG_X26 135 REG_S11 = REG_X27 136 REG_T3 = REG_X28 137 REG_T4 = REG_X29 138 REG_T5 = REG_X30 139 REG_T6 = REG_X31 // aka REG_TMP 140 141 // Go runtime register names. 142 REG_G = REG_TP // G pointer. 143 REG_CTXT = REG_S4 // Context for closures. 144 REG_LR = REG_RA // Link register. 145 REG_TMP = REG_T6 // Reserved for assembler use. 146 147 // ABI names for floating point registers. 148 REG_FT0 = REG_F0 149 REG_FT1 = REG_F1 150 REG_FT2 = REG_F2 151 REG_FT3 = REG_F3 152 REG_FT4 = REG_F4 153 REG_FT5 = REG_F5 154 REG_FT6 = REG_F6 155 REG_FT7 = REG_F7 156 REG_FS0 = REG_F8 157 REG_FS1 = REG_F9 158 REG_FA0 = REG_F10 159 REG_FA1 = REG_F11 160 REG_FA2 = REG_F12 161 REG_FA3 = REG_F13 162 REG_FA4 = REG_F14 163 REG_FA5 = REG_F15 164 REG_FA6 = REG_F16 165 REG_FA7 = REG_F17 166 REG_FS2 = REG_F18 167 REG_FS3 = REG_F19 168 REG_FS4 = REG_F20 169 REG_FS5 = REG_F21 170 REG_FS6 = REG_F22 171 REG_FS7 = REG_F23 172 REG_FS8 = REG_F24 173 REG_FS9 = REG_F25 174 REG_FS10 = REG_F26 175 REG_FS11 = REG_F27 176 REG_FT8 = REG_F28 177 REG_FT9 = REG_F29 178 REG_FT10 = REG_F30 179 REG_FT11 = REG_F31 180 181 // Names generated by the SSA compiler. 182 REGSP = REG_SP 183 REGG = REG_G 184 ) 185 186 // https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#dwarf-register-numbers 187 var RISCV64DWARFRegisters = map[int16]int16{ 188 // Integer Registers. 189 REG_X0: 0, 190 REG_X1: 1, 191 REG_X2: 2, 192 REG_X3: 3, 193 REG_X4: 4, 194 REG_X5: 5, 195 REG_X6: 6, 196 REG_X7: 7, 197 REG_X8: 8, 198 REG_X9: 9, 199 REG_X10: 10, 200 REG_X11: 11, 201 REG_X12: 12, 202 REG_X13: 13, 203 REG_X14: 14, 204 REG_X15: 15, 205 REG_X16: 16, 206 REG_X17: 17, 207 REG_X18: 18, 208 REG_X19: 19, 209 REG_X20: 20, 210 REG_X21: 21, 211 REG_X22: 22, 212 REG_X23: 23, 213 REG_X24: 24, 214 REG_X25: 25, 215 REG_X26: 26, 216 REG_X27: 27, 217 REG_X28: 28, 218 REG_X29: 29, 219 REG_X30: 30, 220 REG_X31: 31, 221 222 // Floating-Point Registers. 223 REG_F0: 32, 224 REG_F1: 33, 225 REG_F2: 34, 226 REG_F3: 35, 227 REG_F4: 36, 228 REG_F5: 37, 229 REG_F6: 38, 230 REG_F7: 39, 231 REG_F8: 40, 232 REG_F9: 41, 233 REG_F10: 42, 234 REG_F11: 43, 235 REG_F12: 44, 236 REG_F13: 45, 237 REG_F14: 46, 238 REG_F15: 47, 239 REG_F16: 48, 240 REG_F17: 49, 241 REG_F18: 50, 242 REG_F19: 51, 243 REG_F20: 52, 244 REG_F21: 53, 245 REG_F22: 54, 246 REG_F23: 55, 247 REG_F24: 56, 248 REG_F25: 57, 249 REG_F26: 58, 250 REG_F27: 59, 251 REG_F28: 60, 252 REG_F29: 61, 253 REG_F30: 62, 254 REG_F31: 63, 255 } 256 257 // Prog.Mark flags. 258 const ( 259 // NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that 260 // it is the first instruction in an AUIPC + I-type pair that needs a 261 // R_RISCV_PCREL_ITYPE relocation. 262 NEED_PCREL_ITYPE_RELOC = 1 << 0 263 264 // NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that 265 // it is the first instruction in an AUIPC + S-type pair that needs a 266 // R_RISCV_PCREL_STYPE relocation. 267 NEED_PCREL_STYPE_RELOC = 1 << 1 268 ) 269 270 // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files 271 // from: 272 // 273 // https://github.com/riscv/riscv-opcodes 274 // 275 // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. 276 // 277 // See also "The RISC-V Instruction Set Manual" at: 278 // 279 // https://riscv.org/specifications/ 280 // 281 // If you modify this table, you MUST run 'go generate' to regenerate anames.go! 282 const ( 283 // Unprivileged ISA (Document Version 20190608-Base-Ratified) 284 285 // 2.4: Integer Computational Instructions 286 AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota 287 ASLTI 288 ASLTIU 289 AANDI 290 AORI 291 AXORI 292 ASLLI 293 ASRLI 294 ASRAI 295 ALUI 296 AAUIPC 297 AADD 298 ASLT 299 ASLTU 300 AAND 301 AOR 302 AXOR 303 ASLL 304 ASRL 305 ASUB 306 ASRA 307 308 // The SLL/SRL/SRA instructions differ slightly between RV32 and RV64, 309 // hence there are pseudo-opcodes for the RV32 specific versions. 310 ASLLIRV32 311 ASRLIRV32 312 ASRAIRV32 313 314 // 2.5: Control Transfer Instructions 315 AJAL 316 AJALR 317 ABEQ 318 ABNE 319 ABLT 320 ABLTU 321 ABGE 322 ABGEU 323 324 // 2.6: Load and Store Instructions 325 ALW 326 ALWU 327 ALH 328 ALHU 329 ALB 330 ALBU 331 ASW 332 ASH 333 ASB 334 335 // 2.7: Memory Ordering Instructions 336 AFENCE 337 AFENCEI 338 AFENCETSO 339 340 // 5.2: Integer Computational Instructions (RV64I) 341 AADDIW 342 ASLLIW 343 ASRLIW 344 ASRAIW 345 AADDW 346 ASLLW 347 ASRLW 348 ASUBW 349 ASRAW 350 351 // 5.3: Load and Store Instructions (RV64I) 352 ALD 353 ASD 354 355 // 7.1: Multiplication Operations 356 AMUL 357 AMULH 358 AMULHU 359 AMULHSU 360 AMULW 361 ADIV 362 ADIVU 363 AREM 364 AREMU 365 ADIVW 366 ADIVUW 367 AREMW 368 AREMUW 369 370 // 8.2: Load-Reserved/Store-Conditional Instructions 371 ALRD 372 ASCD 373 ALRW 374 ASCW 375 376 // 8.3: Atomic Memory Operations 377 AAMOSWAPD 378 AAMOADDD 379 AAMOANDD 380 AAMOORD 381 AAMOXORD 382 AAMOMAXD 383 AAMOMAXUD 384 AAMOMIND 385 AAMOMINUD 386 AAMOSWAPW 387 AAMOADDW 388 AAMOANDW 389 AAMOORW 390 AAMOXORW 391 AAMOMAXW 392 AAMOMAXUW 393 AAMOMINW 394 AAMOMINUW 395 396 // 10.1: Base Counters and Timers 397 ARDCYCLE 398 ARDCYCLEH 399 ARDTIME 400 ARDTIMEH 401 ARDINSTRET 402 ARDINSTRETH 403 404 // 11.2: Floating-Point Control and Status Register 405 AFRCSR 406 AFSCSR 407 AFRRM 408 AFSRM 409 AFRFLAGS 410 AFSFLAGS 411 AFSRMI 412 AFSFLAGSI 413 414 // 11.5: Single-Precision Load and Store Instructions 415 AFLW 416 AFSW 417 418 // 11.6: Single-Precision Floating-Point Computational Instructions 419 AFADDS 420 AFSUBS 421 AFMULS 422 AFDIVS 423 AFMINS 424 AFMAXS 425 AFSQRTS 426 AFMADDS 427 AFMSUBS 428 AFNMADDS 429 AFNMSUBS 430 431 // 11.7: Single-Precision Floating-Point Conversion and Move Instructions 432 AFCVTWS 433 AFCVTLS 434 AFCVTSW 435 AFCVTSL 436 AFCVTWUS 437 AFCVTLUS 438 AFCVTSWU 439 AFCVTSLU 440 AFSGNJS 441 AFSGNJNS 442 AFSGNJXS 443 AFMVXS 444 AFMVSX 445 AFMVXW 446 AFMVWX 447 448 // 11.8: Single-Precision Floating-Point Compare Instructions 449 AFEQS 450 AFLTS 451 AFLES 452 453 // 11.9: Single-Precision Floating-Point Classify Instruction 454 AFCLASSS 455 456 // 12.3: Double-Precision Load and Store Instructions 457 AFLD 458 AFSD 459 460 // 12.4: Double-Precision Floating-Point Computational Instructions 461 AFADDD 462 AFSUBD 463 AFMULD 464 AFDIVD 465 AFMIND 466 AFMAXD 467 AFSQRTD 468 AFMADDD 469 AFMSUBD 470 AFNMADDD 471 AFNMSUBD 472 473 // 12.5: Double-Precision Floating-Point Conversion and Move Instructions 474 AFCVTWD 475 AFCVTLD 476 AFCVTDW 477 AFCVTDL 478 AFCVTWUD 479 AFCVTLUD 480 AFCVTDWU 481 AFCVTDLU 482 AFCVTSD 483 AFCVTDS 484 AFSGNJD 485 AFSGNJND 486 AFSGNJXD 487 AFMVXD 488 AFMVDX 489 490 // 12.6: Double-Precision Floating-Point Compare Instructions 491 AFEQD 492 AFLTD 493 AFLED 494 495 // 12.7: Double-Precision Floating-Point Classify Instruction 496 AFCLASSD 497 498 // 13.1 Quad-Precision Load and Store Instructions 499 AFLQ 500 AFSQ 501 502 // 13.2: Quad-Precision Computational Instructions 503 AFADDQ 504 AFSUBQ 505 AFMULQ 506 AFDIVQ 507 AFMINQ 508 AFMAXQ 509 AFSQRTQ 510 AFMADDQ 511 AFMSUBQ 512 AFNMADDQ 513 AFNMSUBQ 514 515 // 13.3 Quad-Precision Convert and Move Instructions 516 AFCVTWQ 517 AFCVTLQ 518 AFCVTSQ 519 AFCVTDQ 520 AFCVTQW 521 AFCVTQL 522 AFCVTQS 523 AFCVTQD 524 AFCVTWUQ 525 AFCVTLUQ 526 AFCVTQWU 527 AFCVTQLU 528 AFSGNJQ 529 AFSGNJNQ 530 AFSGNJXQ 531 AFMVXQ 532 AFMVQX 533 534 // 13.4 Quad-Precision Floating-Point Compare Instructions 535 AFEQQ 536 AFLEQ 537 AFLTQ 538 539 // 13.5 Quad-Precision Floating-Point Classify Instruction 540 AFCLASSQ 541 542 // Privileged ISA (Version 20190608-Priv-MSU-Ratified) 543 544 // 3.1.9: Instructions to Access CSRs 545 ACSRRW 546 ACSRRS 547 ACSRRC 548 ACSRRWI 549 ACSRRSI 550 ACSRRCI 551 552 // 3.2.1: Environment Call and Breakpoint 553 AECALL 554 ASCALL 555 AEBREAK 556 ASBREAK 557 558 // 3.2.2: Trap-Return Instructions 559 AMRET 560 ASRET 561 AURET 562 ADRET 563 564 // 3.2.3: Wait for Interrupt 565 AWFI 566 567 // 4.2.1: Supervisor Memory-Management Fence Instruction 568 ASFENCEVMA 569 570 // Hypervisor Memory-Management Instructions 571 AHFENCEGVMA 572 AHFENCEVVMA 573 574 // The escape hatch. Inserts a single 32-bit word. 575 AWORD 576 577 // Pseudo-instructions. These get translated by the assembler into other 578 // instructions, based on their operands. 579 ABEQZ 580 ABGEZ 581 ABGT 582 ABGTU 583 ABGTZ 584 ABLE 585 ABLEU 586 ABLEZ 587 ABLTZ 588 ABNEZ 589 AFNEGD 590 AFNEGS 591 AFNED 592 AFNES 593 AMOV 594 AMOVB 595 AMOVBU 596 AMOVF 597 AMOVD 598 AMOVH 599 AMOVHU 600 AMOVW 601 AMOVWU 602 ANEG 603 ANEGW 604 ANOT 605 ASEQZ 606 ASNEZ 607 608 // End marker 609 ALAST 610 ) 611 612 // All unary instructions which write to their arguments (as opposed to reading 613 // from them) go here. The assembly parser uses this information to populate 614 // its AST in a semantically reasonable way. 615 // 616 // Any instructions not listed here are assumed to either be non-unary or to read 617 // from its argument. 618 var unaryDst = map[obj.As]bool{ 619 ARDCYCLE: true, 620 ARDCYCLEH: true, 621 ARDTIME: true, 622 ARDTIMEH: true, 623 ARDINSTRET: true, 624 ARDINSTRETH: true, 625 } 626 627 // Instruction encoding masks. 628 const ( 629 // ITypeImmMask is a mask including only the immediate portion of 630 // I-type instructions. 631 ITypeImmMask = 0xfff00000 632 633 // STypeImmMask is a mask including only the immediate portion of 634 // S-type instructions. 635 STypeImmMask = 0xfe000f80 636 637 // UTypeImmMask is a mask including only the immediate portion of 638 // U-type instructions. 639 UTypeImmMask = 0xfffff000 640 641 // UJTypeImmMask is a mask including only the immediate portion of 642 // UJ-type instructions. 643 UJTypeImmMask = UTypeImmMask 644 )