a.out.go (15404B)
1 // cmd/7c/7.out.h from Vita Nuova. 2 // https://code.google.com/p/ken-cc/source/browse/src/cmd/7c/7.out.h 3 // 4 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6 // Portions Copyright © 1997-1999 Vita Nuova Limited 7 // Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8 // Portions Copyright © 2004,2006 Bruce Ellis 9 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10 // Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11 // Portions Copyright © 2009 The Go Authors. All rights reserved. 12 // 13 // Permission is hereby granted, free of charge, to any person obtaining a copy 14 // of this software and associated documentation files (the "Software"), to deal 15 // in the Software without restriction, including without limitation the rights 16 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 // copies of the Software, and to permit persons to whom the Software is 18 // furnished to do so, subject to the following conditions: 19 // 20 // The above copyright notice and this permission notice shall be included in 21 // all copies or substantial portions of the Software. 22 // 23 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 // THE SOFTWARE. 30 31 package arm64 32 33 import "github.com/twitchyliquid64/golang-asm/obj" 34 35 const ( 36 NSNAME = 8 37 NSYM = 50 38 NREG = 32 /* number of general registers */ 39 NFREG = 32 /* number of floating point registers */ 40 ) 41 42 // General purpose registers, kept in the low bits of Prog.Reg. 43 const ( 44 // integer 45 REG_R0 = obj.RBaseARM64 + iota 46 REG_R1 47 REG_R2 48 REG_R3 49 REG_R4 50 REG_R5 51 REG_R6 52 REG_R7 53 REG_R8 54 REG_R9 55 REG_R10 56 REG_R11 57 REG_R12 58 REG_R13 59 REG_R14 60 REG_R15 61 REG_R16 62 REG_R17 63 REG_R18 64 REG_R19 65 REG_R20 66 REG_R21 67 REG_R22 68 REG_R23 69 REG_R24 70 REG_R25 71 REG_R26 72 REG_R27 73 REG_R28 74 REG_R29 75 REG_R30 76 REG_R31 77 78 // scalar floating point 79 REG_F0 80 REG_F1 81 REG_F2 82 REG_F3 83 REG_F4 84 REG_F5 85 REG_F6 86 REG_F7 87 REG_F8 88 REG_F9 89 REG_F10 90 REG_F11 91 REG_F12 92 REG_F13 93 REG_F14 94 REG_F15 95 REG_F16 96 REG_F17 97 REG_F18 98 REG_F19 99 REG_F20 100 REG_F21 101 REG_F22 102 REG_F23 103 REG_F24 104 REG_F25 105 REG_F26 106 REG_F27 107 REG_F28 108 REG_F29 109 REG_F30 110 REG_F31 111 112 // SIMD 113 REG_V0 114 REG_V1 115 REG_V2 116 REG_V3 117 REG_V4 118 REG_V5 119 REG_V6 120 REG_V7 121 REG_V8 122 REG_V9 123 REG_V10 124 REG_V11 125 REG_V12 126 REG_V13 127 REG_V14 128 REG_V15 129 REG_V16 130 REG_V17 131 REG_V18 132 REG_V19 133 REG_V20 134 REG_V21 135 REG_V22 136 REG_V23 137 REG_V24 138 REG_V25 139 REG_V26 140 REG_V27 141 REG_V28 142 REG_V29 143 REG_V30 144 REG_V31 145 146 // The EQ in 147 // CSET EQ, R0 148 // is encoded as TYPE_REG, even though it's not really a register. 149 COND_EQ 150 COND_NE 151 COND_HS 152 COND_LO 153 COND_MI 154 COND_PL 155 COND_VS 156 COND_VC 157 COND_HI 158 COND_LS 159 COND_GE 160 COND_LT 161 COND_GT 162 COND_LE 163 COND_AL 164 COND_NV 165 166 REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31 167 ) 168 169 // bits 0-4 indicates register: Vn 170 // bits 5-8 indicates arrangement: <T> 171 const ( 172 REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T> 173 REG_ELEM // Vn.<T>[index] 174 REG_ELEM_END 175 ) 176 177 // Not registers, but flags that can be combined with regular register 178 // constants to indicate extended register conversion. When checking, 179 // you should subtract obj.RBaseARM64 first. From this difference, bit 11 180 // indicates extended register, bits 8-10 select the conversion mode. 181 // REG_LSL is the index shift specifier, bit 9 indicates shifted offset register. 182 const REG_LSL = obj.RBaseARM64 + 1<<9 183 const REG_EXT = obj.RBaseARM64 + 1<<11 184 185 const ( 186 REG_UXTB = REG_EXT + iota<<8 187 REG_UXTH 188 REG_UXTW 189 REG_UXTX 190 REG_SXTB 191 REG_SXTH 192 REG_SXTW 193 REG_SXTX 194 ) 195 196 // Special registers, after subtracting obj.RBaseARM64, bit 12 indicates 197 // a special register and the low bits select the register. 198 // SYSREG_END is the last item in the automatically generated system register 199 // declaration, and it is defined in the sysRegEnc.go file. 200 const ( 201 REG_SPECIAL = obj.RBaseARM64 + 1<<12 202 REG_DAIFSet = SYSREG_END + iota 203 REG_DAIFClr 204 REG_PLDL1KEEP 205 REG_PLDL1STRM 206 REG_PLDL2KEEP 207 REG_PLDL2STRM 208 REG_PLDL3KEEP 209 REG_PLDL3STRM 210 REG_PLIL1KEEP 211 REG_PLIL1STRM 212 REG_PLIL2KEEP 213 REG_PLIL2STRM 214 REG_PLIL3KEEP 215 REG_PLIL3STRM 216 REG_PSTL1KEEP 217 REG_PSTL1STRM 218 REG_PSTL2KEEP 219 REG_PSTL2STRM 220 REG_PSTL3KEEP 221 REG_PSTL3STRM 222 ) 223 224 // Register assignments: 225 // 226 // compiler allocates R0 up as temps 227 // compiler allocates register variables R7-R25 228 // compiler allocates external registers R26 down 229 // 230 // compiler allocates register variables F7-F26 231 // compiler allocates external registers F26 down 232 const ( 233 REGMIN = REG_R7 // register variables allocated from here to REGMAX 234 REGRT1 = REG_R16 // ARM64 IP0, external linker may use as a scrach register in trampoline 235 REGRT2 = REG_R17 // ARM64 IP1, external linker may use as a scrach register in trampoline 236 REGPR = REG_R18 // ARM64 platform register, unused in the Go toolchain 237 REGMAX = REG_R25 238 239 REGCTXT = REG_R26 // environment for closures 240 REGTMP = REG_R27 // reserved for liblink 241 REGG = REG_R28 // G 242 REGFP = REG_R29 // frame pointer, unused in the Go toolchain 243 REGLINK = REG_R30 244 245 // ARM64 uses R31 as both stack pointer and zero register, 246 // depending on the instruction. To differentiate RSP from ZR, 247 // we use a different numeric value for REGZERO and REGSP. 248 REGZERO = REG_R31 249 REGSP = REG_RSP 250 251 FREGRET = REG_F0 252 FREGMIN = REG_F7 // first register variable 253 FREGMAX = REG_F26 // last register variable for 7g only 254 FREGEXT = REG_F26 // first external register 255 ) 256 257 // http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf 258 var ARM64DWARFRegisters = map[int16]int16{ 259 REG_R0: 0, 260 REG_R1: 1, 261 REG_R2: 2, 262 REG_R3: 3, 263 REG_R4: 4, 264 REG_R5: 5, 265 REG_R6: 6, 266 REG_R7: 7, 267 REG_R8: 8, 268 REG_R9: 9, 269 REG_R10: 10, 270 REG_R11: 11, 271 REG_R12: 12, 272 REG_R13: 13, 273 REG_R14: 14, 274 REG_R15: 15, 275 REG_R16: 16, 276 REG_R17: 17, 277 REG_R18: 18, 278 REG_R19: 19, 279 REG_R20: 20, 280 REG_R21: 21, 281 REG_R22: 22, 282 REG_R23: 23, 283 REG_R24: 24, 284 REG_R25: 25, 285 REG_R26: 26, 286 REG_R27: 27, 287 REG_R28: 28, 288 REG_R29: 29, 289 REG_R30: 30, 290 291 // floating point 292 REG_F0: 64, 293 REG_F1: 65, 294 REG_F2: 66, 295 REG_F3: 67, 296 REG_F4: 68, 297 REG_F5: 69, 298 REG_F6: 70, 299 REG_F7: 71, 300 REG_F8: 72, 301 REG_F9: 73, 302 REG_F10: 74, 303 REG_F11: 75, 304 REG_F12: 76, 305 REG_F13: 77, 306 REG_F14: 78, 307 REG_F15: 79, 308 REG_F16: 80, 309 REG_F17: 81, 310 REG_F18: 82, 311 REG_F19: 83, 312 REG_F20: 84, 313 REG_F21: 85, 314 REG_F22: 86, 315 REG_F23: 87, 316 REG_F24: 88, 317 REG_F25: 89, 318 REG_F26: 90, 319 REG_F27: 91, 320 REG_F28: 92, 321 REG_F29: 93, 322 REG_F30: 94, 323 REG_F31: 95, 324 325 // SIMD 326 REG_V0: 64, 327 REG_V1: 65, 328 REG_V2: 66, 329 REG_V3: 67, 330 REG_V4: 68, 331 REG_V5: 69, 332 REG_V6: 70, 333 REG_V7: 71, 334 REG_V8: 72, 335 REG_V9: 73, 336 REG_V10: 74, 337 REG_V11: 75, 338 REG_V12: 76, 339 REG_V13: 77, 340 REG_V14: 78, 341 REG_V15: 79, 342 REG_V16: 80, 343 REG_V17: 81, 344 REG_V18: 82, 345 REG_V19: 83, 346 REG_V20: 84, 347 REG_V21: 85, 348 REG_V22: 86, 349 REG_V23: 87, 350 REG_V24: 88, 351 REG_V25: 89, 352 REG_V26: 90, 353 REG_V27: 91, 354 REG_V28: 92, 355 REG_V29: 93, 356 REG_V30: 94, 357 REG_V31: 95, 358 } 359 360 const ( 361 BIG = 2048 - 8 362 ) 363 364 const ( 365 /* mark flags */ 366 LABEL = 1 << iota 367 LEAF 368 FLOAT 369 BRANCH 370 LOAD 371 FCMP 372 SYNC 373 LIST 374 FOLL 375 NOSCHED 376 ) 377 378 const ( 379 // optab is sorted based on the order of these constants 380 // and the first match is chosen. 381 // The more specific class needs to come earlier. 382 C_NONE = iota 383 C_REG // R0..R30 384 C_RSP // R0..R30, RSP 385 C_FREG // F0..F31 386 C_VREG // V0..V31 387 C_PAIR // (Rn, Rm) 388 C_SHIFT // Rn<<2 389 C_EXTREG // Rn.UXTB[<<3] 390 C_SPR // REG_NZCV 391 C_COND // EQ, NE, etc 392 C_ARNG // Vn.<T> 393 C_ELEM // Vn.<T>[index] 394 C_LIST // [V1, V2, V3] 395 396 C_ZCON // $0 or ZR 397 C_ABCON0 // could be C_ADDCON0 or C_BITCON 398 C_ADDCON0 // 12-bit unsigned, unshifted 399 C_ABCON // could be C_ADDCON or C_BITCON 400 C_AMCON // could be C_ADDCON or C_MOVCON 401 C_ADDCON // 12-bit unsigned, shifted left by 0 or 12 402 C_MBCON // could be C_MOVCON or C_BITCON 403 C_MOVCON // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16 404 C_BITCON // bitfield and logical immediate masks 405 C_ADDCON2 // 24-bit constant 406 C_LCON // 32-bit constant 407 C_MOVCON2 // a constant that can be loaded with one MOVZ/MOVN and one MOVK 408 C_MOVCON3 // a constant that can be loaded with one MOVZ/MOVN and two MOVKs 409 C_VCON // 64-bit constant 410 C_FCON // floating-point constant 411 C_VCONADDR // 64-bit memory address 412 413 C_AACON // ADDCON offset in auto constant $a(FP) 414 C_AACON2 // 24-bit offset in auto constant $a(FP) 415 C_LACON // 32-bit offset in auto constant $a(FP) 416 C_AECON // ADDCON offset in extern constant $e(SB) 417 418 // TODO(aram): only one branch class should be enough 419 C_SBRA // for TYPE_BRANCH 420 C_LBRA 421 422 C_ZAUTO // 0(RSP) 423 C_NSAUTO_8 // -256 <= x < 0, 0 mod 8 424 C_NSAUTO_4 // -256 <= x < 0, 0 mod 4 425 C_NSAUTO // -256 <= x < 0 426 C_NPAUTO // -512 <= x < 0, 0 mod 8 427 C_NAUTO4K // -4095 <= x < 0 428 C_PSAUTO_8 // 0 to 255, 0 mod 8 429 C_PSAUTO_4 // 0 to 255, 0 mod 4 430 C_PSAUTO // 0 to 255 431 C_PPAUTO // 0 to 504, 0 mod 8 432 C_UAUTO4K_8 // 0 to 4095, 0 mod 8 433 C_UAUTO4K_4 // 0 to 4095, 0 mod 4 434 C_UAUTO4K_2 // 0 to 4095, 0 mod 2 435 C_UAUTO4K // 0 to 4095 436 C_UAUTO8K_8 // 0 to 8190, 0 mod 8 437 C_UAUTO8K_4 // 0 to 8190, 0 mod 4 438 C_UAUTO8K // 0 to 8190, 0 mod 2 439 C_UAUTO16K_8 // 0 to 16380, 0 mod 8 440 C_UAUTO16K // 0 to 16380, 0 mod 4 441 C_UAUTO32K // 0 to 32760, 0 mod 8 442 C_LAUTO // any other 32-bit constant 443 444 C_SEXT1 // 0 to 4095, direct 445 C_SEXT2 // 0 to 8190 446 C_SEXT4 // 0 to 16380 447 C_SEXT8 // 0 to 32760 448 C_SEXT16 // 0 to 65520 449 C_LEXT 450 451 C_ZOREG // 0(R) 452 C_NSOREG_8 // must mirror C_NSAUTO_8, etc 453 C_NSOREG_4 454 C_NSOREG 455 C_NPOREG 456 C_NOREG4K 457 C_PSOREG_8 458 C_PSOREG_4 459 C_PSOREG 460 C_PPOREG 461 C_UOREG4K_8 462 C_UOREG4K_4 463 C_UOREG4K_2 464 C_UOREG4K 465 C_UOREG8K_8 466 C_UOREG8K_4 467 C_UOREG8K 468 C_UOREG16K_8 469 C_UOREG16K 470 C_UOREG32K 471 C_LOREG 472 473 C_ADDR // TODO(aram): explain difference from C_VCONADDR 474 475 // The GOT slot for a symbol in -dynlink mode. 476 C_GOTADDR 477 478 // TLS "var" in local exec mode: will become a constant offset from 479 // thread local base that is ultimately chosen by the program linker. 480 C_TLS_LE 481 482 // TLS "var" in initial exec mode: will become a memory address (chosen 483 // by the program linker) that the dynamic linker will fill with the 484 // offset from the thread local base. 485 C_TLS_IE 486 487 C_ROFF // register offset (including register extended) 488 489 C_GOK 490 C_TEXTSIZE 491 C_NCLASS // must be last 492 ) 493 494 const ( 495 C_XPRE = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it 496 C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it 497 ) 498 499 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64 500 501 const ( 502 AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota 503 AADCS 504 AADCSW 505 AADCW 506 AADD 507 AADDS 508 AADDSW 509 AADDW 510 AADR 511 AADRP 512 AAND 513 AANDS 514 AANDSW 515 AANDW 516 AASR 517 AASRW 518 AAT 519 ABFI 520 ABFIW 521 ABFM 522 ABFMW 523 ABFXIL 524 ABFXILW 525 ABIC 526 ABICS 527 ABICSW 528 ABICW 529 ABRK 530 ACBNZ 531 ACBNZW 532 ACBZ 533 ACBZW 534 ACCMN 535 ACCMNW 536 ACCMP 537 ACCMPW 538 ACINC 539 ACINCW 540 ACINV 541 ACINVW 542 ACLREX 543 ACLS 544 ACLSW 545 ACLZ 546 ACLZW 547 ACMN 548 ACMNW 549 ACMP 550 ACMPW 551 ACNEG 552 ACNEGW 553 ACRC32B 554 ACRC32CB 555 ACRC32CH 556 ACRC32CW 557 ACRC32CX 558 ACRC32H 559 ACRC32W 560 ACRC32X 561 ACSEL 562 ACSELW 563 ACSET 564 ACSETM 565 ACSETMW 566 ACSETW 567 ACSINC 568 ACSINCW 569 ACSINV 570 ACSINVW 571 ACSNEG 572 ACSNEGW 573 ADC 574 ADCPS1 575 ADCPS2 576 ADCPS3 577 ADMB 578 ADRPS 579 ADSB 580 AEON 581 AEONW 582 AEOR 583 AEORW 584 AERET 585 AEXTR 586 AEXTRW 587 AHINT 588 AHLT 589 AHVC 590 AIC 591 AISB 592 ALDADDAB 593 ALDADDAD 594 ALDADDAH 595 ALDADDAW 596 ALDADDALB 597 ALDADDALD 598 ALDADDALH 599 ALDADDALW 600 ALDADDB 601 ALDADDD 602 ALDADDH 603 ALDADDW 604 ALDADDLB 605 ALDADDLD 606 ALDADDLH 607 ALDADDLW 608 ALDANDAB 609 ALDANDAD 610 ALDANDAH 611 ALDANDAW 612 ALDANDALB 613 ALDANDALD 614 ALDANDALH 615 ALDANDALW 616 ALDANDB 617 ALDANDD 618 ALDANDH 619 ALDANDW 620 ALDANDLB 621 ALDANDLD 622 ALDANDLH 623 ALDANDLW 624 ALDAR 625 ALDARB 626 ALDARH 627 ALDARW 628 ALDAXP 629 ALDAXPW 630 ALDAXR 631 ALDAXRB 632 ALDAXRH 633 ALDAXRW 634 ALDEORAB 635 ALDEORAD 636 ALDEORAH 637 ALDEORAW 638 ALDEORALB 639 ALDEORALD 640 ALDEORALH 641 ALDEORALW 642 ALDEORB 643 ALDEORD 644 ALDEORH 645 ALDEORW 646 ALDEORLB 647 ALDEORLD 648 ALDEORLH 649 ALDEORLW 650 ALDORAB 651 ALDORAD 652 ALDORAH 653 ALDORAW 654 ALDORALB 655 ALDORALD 656 ALDORALH 657 ALDORALW 658 ALDORB 659 ALDORD 660 ALDORH 661 ALDORW 662 ALDORLB 663 ALDORLD 664 ALDORLH 665 ALDORLW 666 ALDP 667 ALDPW 668 ALDPSW 669 ALDXR 670 ALDXRB 671 ALDXRH 672 ALDXRW 673 ALDXP 674 ALDXPW 675 ALSL 676 ALSLW 677 ALSR 678 ALSRW 679 AMADD 680 AMADDW 681 AMNEG 682 AMNEGW 683 AMOVK 684 AMOVKW 685 AMOVN 686 AMOVNW 687 AMOVZ 688 AMOVZW 689 AMRS 690 AMSR 691 AMSUB 692 AMSUBW 693 AMUL 694 AMULW 695 AMVN 696 AMVNW 697 ANEG 698 ANEGS 699 ANEGSW 700 ANEGW 701 ANGC 702 ANGCS 703 ANGCSW 704 ANGCW 705 ANOOP 706 AORN 707 AORNW 708 AORR 709 AORRW 710 APRFM 711 APRFUM 712 ARBIT 713 ARBITW 714 AREM 715 AREMW 716 AREV 717 AREV16 718 AREV16W 719 AREV32 720 AREVW 721 AROR 722 ARORW 723 ASBC 724 ASBCS 725 ASBCSW 726 ASBCW 727 ASBFIZ 728 ASBFIZW 729 ASBFM 730 ASBFMW 731 ASBFX 732 ASBFXW 733 ASDIV 734 ASDIVW 735 ASEV 736 ASEVL 737 ASMADDL 738 ASMC 739 ASMNEGL 740 ASMSUBL 741 ASMULH 742 ASMULL 743 ASTXR 744 ASTXRB 745 ASTXRH 746 ASTXP 747 ASTXPW 748 ASTXRW 749 ASTLP 750 ASTLPW 751 ASTLR 752 ASTLRB 753 ASTLRH 754 ASTLRW 755 ASTLXP 756 ASTLXPW 757 ASTLXR 758 ASTLXRB 759 ASTLXRH 760 ASTLXRW 761 ASTP 762 ASTPW 763 ASUB 764 ASUBS 765 ASUBSW 766 ASUBW 767 ASVC 768 ASXTB 769 ASXTBW 770 ASXTH 771 ASXTHW 772 ASXTW 773 ASYS 774 ASYSL 775 ATBNZ 776 ATBZ 777 ATLBI 778 ATST 779 ATSTW 780 AUBFIZ 781 AUBFIZW 782 AUBFM 783 AUBFMW 784 AUBFX 785 AUBFXW 786 AUDIV 787 AUDIVW 788 AUMADDL 789 AUMNEGL 790 AUMSUBL 791 AUMULH 792 AUMULL 793 AUREM 794 AUREMW 795 AUXTB 796 AUXTH 797 AUXTW 798 AUXTBW 799 AUXTHW 800 AWFE 801 AWFI 802 AYIELD 803 AMOVB 804 AMOVBU 805 AMOVH 806 AMOVHU 807 AMOVW 808 AMOVWU 809 AMOVD 810 AMOVNP 811 AMOVNPW 812 AMOVP 813 AMOVPD 814 AMOVPQ 815 AMOVPS 816 AMOVPSW 817 AMOVPW 818 ASWPAD 819 ASWPAW 820 ASWPAH 821 ASWPAB 822 ASWPALD 823 ASWPALW 824 ASWPALH 825 ASWPALB 826 ASWPD 827 ASWPW 828 ASWPH 829 ASWPB 830 ASWPLD 831 ASWPLW 832 ASWPLH 833 ASWPLB 834 ABEQ 835 ABNE 836 ABCS 837 ABHS 838 ABCC 839 ABLO 840 ABMI 841 ABPL 842 ABVS 843 ABVC 844 ABHI 845 ABLS 846 ABGE 847 ABLT 848 ABGT 849 ABLE 850 AFABSD 851 AFABSS 852 AFADDD 853 AFADDS 854 AFCCMPD 855 AFCCMPED 856 AFCCMPS 857 AFCCMPES 858 AFCMPD 859 AFCMPED 860 AFCMPES 861 AFCMPS 862 AFCVTSD 863 AFCVTDS 864 AFCVTZSD 865 AFCVTZSDW 866 AFCVTZSS 867 AFCVTZSSW 868 AFCVTZUD 869 AFCVTZUDW 870 AFCVTZUS 871 AFCVTZUSW 872 AFDIVD 873 AFDIVS 874 AFLDPD 875 AFLDPS 876 AFMOVD 877 AFMOVS 878 AFMOVQ 879 AFMULD 880 AFMULS 881 AFNEGD 882 AFNEGS 883 AFSQRTD 884 AFSQRTS 885 AFSTPD 886 AFSTPS 887 AFSUBD 888 AFSUBS 889 ASCVTFD 890 ASCVTFS 891 ASCVTFWD 892 ASCVTFWS 893 AUCVTFD 894 AUCVTFS 895 AUCVTFWD 896 AUCVTFWS 897 AWORD 898 ADWORD 899 AFCSELS 900 AFCSELD 901 AFMAXS 902 AFMINS 903 AFMAXD 904 AFMIND 905 AFMAXNMS 906 AFMAXNMD 907 AFNMULS 908 AFNMULD 909 AFRINTNS 910 AFRINTND 911 AFRINTPS 912 AFRINTPD 913 AFRINTMS 914 AFRINTMD 915 AFRINTZS 916 AFRINTZD 917 AFRINTAS 918 AFRINTAD 919 AFRINTXS 920 AFRINTXD 921 AFRINTIS 922 AFRINTID 923 AFMADDS 924 AFMADDD 925 AFMSUBS 926 AFMSUBD 927 AFNMADDS 928 AFNMADDD 929 AFNMSUBS 930 AFNMSUBD 931 AFMINNMS 932 AFMINNMD 933 AFCVTDH 934 AFCVTHS 935 AFCVTHD 936 AFCVTSH 937 AAESD 938 AAESE 939 AAESIMC 940 AAESMC 941 ASHA1C 942 ASHA1H 943 ASHA1M 944 ASHA1P 945 ASHA1SU0 946 ASHA1SU1 947 ASHA256H 948 ASHA256H2 949 ASHA256SU0 950 ASHA256SU1 951 ASHA512H 952 ASHA512H2 953 ASHA512SU0 954 ASHA512SU1 955 AVADD 956 AVADDP 957 AVAND 958 AVBIF 959 AVCMEQ 960 AVCNT 961 AVEOR 962 AVMOV 963 AVLD1 964 AVLD2 965 AVLD3 966 AVLD4 967 AVLD1R 968 AVLD2R 969 AVLD3R 970 AVLD4R 971 AVORR 972 AVREV16 973 AVREV32 974 AVREV64 975 AVST1 976 AVST2 977 AVST3 978 AVST4 979 AVDUP 980 AVADDV 981 AVMOVI 982 AVUADDLV 983 AVSUB 984 AVFMLA 985 AVFMLS 986 AVPMULL 987 AVPMULL2 988 AVEXT 989 AVRBIT 990 AVUSHR 991 AVUSHLL 992 AVUSHLL2 993 AVUXTL 994 AVUXTL2 995 AVUZP1 996 AVUZP2 997 AVSHL 998 AVSRI 999 AVBSL 1000 AVBIT 1001 AVTBL 1002 AVZIP1 1003 AVZIP2 1004 AVCMTST 1005 ALAST 1006 AB = obj.AJMP 1007 ABL = obj.ACALL 1008 ) 1009 1010 const ( 1011 // shift types 1012 SHIFT_LL = 0 << 22 1013 SHIFT_LR = 1 << 22 1014 SHIFT_AR = 2 << 22 1015 ) 1016 1017 // Arrangement for ARM64 SIMD instructions 1018 const ( 1019 // arrangement types 1020 ARNG_8B = iota 1021 ARNG_16B 1022 ARNG_1D 1023 ARNG_4H 1024 ARNG_8H 1025 ARNG_2S 1026 ARNG_4S 1027 ARNG_2D 1028 ARNG_1Q 1029 ARNG_B 1030 ARNG_H 1031 ARNG_S 1032 ARNG_D 1033 )